Specification Update

Errata
44 Specification Update
AT77. Writing Shared Unaligned Data that Crosses a Cache Line without
Proper Semaphores or Barriers May Expose a Memory Ordering Issue
Problem: Software which is written so that multiple agents can modify the same shared
unaligned memory location at the same time may experience a memory
ordering issue if multiple loads access this shared data shortly thereafter.
Exposure to this problem requires the use of a data write which spans a
cache line boundary.
Implication: This erratum may cause loads to be observed out of order. Intel has not
observed this erratum with any commercially available software or system.
Workaround: Software should ensure at least one of the following is true when modifying
shared data by multiple agents:
• The shared data is aligned
• Proper semaphores or barriers are used in order to prevent concurrent
data accesses.
Status: For the steppings affected, see the Summary Tables of Changes.
AT78. Update of Read/Write (R/W) or User/Supervisor (U/S) or Present
(P) Bits without TLB Shootdown May Cause Unexpected Processor
Behavior
Problem: Updating a page table entry by changing R/W, U/S or P bits without TLB
shootdown (as defined by the 4 step procedure in "Propagation of Page Table
and Page Directory Entry Changes to Multiple Processors" In volume 3A of the
IA-32 Intel® Architecture Software Developer's Manual), in conjunction with
a complex sequence of internal processor micro-architectural events, may
lead to unexpected processor behavior.
Implication: This erratum may lead to livelock, shutdown or other unexpected processor
behavior. Intel has not observed this erratum with any commercially available
system.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.