Specification Update

Errata

AT46. INIT Does Not Clear Global Entries in the TLB

Problem:

INIT may not flush a TLB entry when:

• The processor is in protected mode with paging enabled and the page global

enable flag is set (PGE bit of CR4 register).

• G bit for the page table entry is set.

• TLB entry is present in TLB when INIT occurs.

Implication: Software may encounter unexpected page fault or incorrect address translation due to

a TLB entry erroneously left in TLB after INIT.

Workaround: Write to CR3, CR4 (setting bits PSE, PGE or PAE) or CR0 (setting bits PG or PE)

registers before writing to memory early in BIOS code to clear all the global entries

from TLB.

Status: For the steppings affected, see the Summary Tables of Changes.

AT47. Using Memory Type Aliasing with Memory Types WB/WT May Lead to

Unpredictable Behavior

Problem:

Memory type aliasing occurs when a single physical page is mapped to two or more

different linear addresses, each with different memory type. Memory type aliasing

with the memory types WB and WT may cause the processor to perform incorrect

operations leading to unpredictable behavior.

Implication: Software that uses aliasing of WB and WT memory types may observe unpredictable

behavior.

Workaround: It is possible for the BIOS to contain a workaround for this erratum.

Status: For the steppings affected, see the Summary Tables of Changes.

AT48. BTS Message May Be Lost When the STPCLK# Signal is Active.

Problem:

STPCLK# is asserted to enable the processor to enter a low-power state. Under some

circumstances, when STPCLK# becomes active, the BTS (Branch Trace Store)

message may be either lost and not written or written with corrupted branch address

to the Debug Store area.

Implication: BTS messages may be lost or be corrupted in the presence of STPCLK# assertions.

Workaround: None Identified.

Status: For the steppings affected, see the Summary Tables of Changes.