Specification Update

Summary Tables of Changes

NO A1 Plan ERRATA

AT83

X No Fix Storage of PEBS Record Delayed Following Execution of MOV SS or STI

AT84

X No Fix Store Ordering May be Incorrect between WC and WP Memory

AT85

X Plan Fix

Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 (30AH) and

MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When the Processor is Reset

AT86

X No Fix

Updating Code Page Directory Attributes without TLB Invalidation May Result in

Improper Handling of Code #PF

AT87

X Plan Fix Performance Monitoring Event BR_INST_RETIRED May Count CPUID Instructions as

Branches

AT88

X No Fix Performance Monitoring Event MISALIGN_MEM_REF May Over Count

AT89

X No Fix A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of

the Monitoring Hardware

AT90

X Plan Fix False Level One Data Cache Parity Machine-Check Exceptions May be Signaled

AT91

X No Fix PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR Information

AT92

X No Fix

A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to

an MTRR Mask

AT93

X No Fix

RSM Instruction Execution under Certain Conditions May Cause Processor Hang or

Unexpected Instruction Execution Results

Number SPECIFICATION CHANGES

- There are no Specification Changes in this Specification Update revision.

Number SPECIFICATION CLARIFICATIONS

AT1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation

Number DOCUMENTATION CHANGES

- There are no Documentation Changes in this Specification Update revision.