Specification Update

Summary Tables of Changes
12 Specification Update
NO A1 Plan ERRATA
AT59
X No Fix PMI May Be Delayed to Next PEBS Event
AT60
X Plan Fix
PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is
Set
AT61
X No Fix Asynchronous MCE During a Far Transfer May Corrupt ESP
AT62
X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
AT63
X No Fix BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts
AT64
X No Fix Performance Monitor SSE Retired Instructions May Return Incorrect Values
AT65
X Plan Fix REP Store Instructions in a Specific Situation may cause the Processor to Hang
AT66
X Plan Fix
Debug Register May Contain Incorrect Information on a MOVSS or POPSS Instruction
Followed by SYSRET
AT67
X No Fix
VM Bit is Cleared on Second Fault Handled by Task Switch from Virtual-8086 (VM86)
AT68
X No Fix
The BS Flag in DR6 May be Set for Non-Single-Step #DB Exception
AT69
X No Fix
Performance Monitoring Events for L1 and L2 Miss May Not be Accurate
AT70
X Plan Fix
CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When
Only Version 1 Capabilities are Available
AT71
X No Fix
Unaligned Accesses to Paging Structures May Cause the Processor to Hang
AT72
X Plan Fix
Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May
Cause Unexpected Processor Behavior
AT73
X Plan Fix
Invalid Instructions May Lead to Unexpected Behavior
AT74
X No Fix
EFLAGS, CR0, CR4 and the EXF4 Signal May be Incorrect after Shutdown
AT75
X Plan Fix
Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some
Decoded Instructions
AT76
X No Fix
Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for
PMULUDQ Instruction
AT77
X No Fix
Writing Shared Unaligned Data that Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a Memory Ordering Issue
AT78
X Plan Fix
Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB
Shootdown May Cause Unexpected Processor Behavior
AT79
X No Fix
Fault on ENTER Instruction May Result in Unexpected Values on Stack Frame
AT80
X No Fix
INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain
Conditions
AT81
X No Fix
Page Access Bit May be Set Prior to Signaling a Code Segment Limit Fault
AT82
X Plan Fix
The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and
SYSRET