Specification Update

Summary Tables of Changes
10 Specification Update
NO A1 Plan ERRATA
AT12
X No Fix Count Value for Performance-Monitoring Counter PMH_PAGE_WALK May be Incorrect
AT13
X No Fix LER MSRs May be Incorrectly Updated
AT14
X No Fix Performance Monitoring Events for Retired Instructions (C0H) May Not be Accurate
AT15
X No Fix
Performance Monitoring Event For Number Of Reference Cycles When The Processor
Is Not Halted (3CH) Does Not Count According To The Specification
AT16
X No Fix
Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address
Translations
AT17
X No Fix Code Segment limit violation may occur on 4 Gigabyte limit check
AT18
X Plan Fix FP Inexact-Result Exception Flag May Not Be Set
AT19
X Plan Fix
Global Pages in the Data Translation Look-Aside Buffer (DTLB) May Not Be Flushed
by RSM instruction before Restoring the Architectural State from SMRAM
AT20
X Plan Fix Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results
AT21
X No Fix
Some Bus Performance Monitoring Events May Not Count Local Events under Certain
Conditions
AT22
X No Fix Premature Execution of a Load Operation Prior to Exception Handler Invocation
AT23
X No Fix
General Protection (#GP) Fault May Not Be Signaled on Data Segment Limit Violation
above 4-G Limit
AT24
X No Fix EIP May be Incorrect after Shutdown in IA-32e Mode
AT25
X No Fix
#GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute
Disable Bit is Not Supported
AT26
X Plan Fix
(E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast
String REP STOS With Large Data Structures
AT27
X Plan Fix
Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired
(C0H) May Not Be Accurate
AT28
X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect
AT29
X Plan Fix
Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction
Execution Results
AT30
X No Fix
MSRs Actual Frequency Clock Count (IA32_APERF) or Maximum Frequency Clock
Count (IA32_MPERF) May Contain Incorrect Data after a Machine Check Exception
(MCE)
AT31
X No Fix
Incorrect Address Computed For Last Byte of FXSAVE/FXRSTOR Image Leads to
Partial Memory Update
AT32
X No Fix Split Locked Stores May not Trigger the Monitoring Hardware
AT33
X Plan Fix
REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >=
0X100000000
AT34
X Plan Fix
FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a
Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause FPU
Instruction or Operand Pointer Corruption