Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

Datasheet 23
Intel
®
Celeron
®
Processor in the 478-Pin Package
NOTES:
1. The loadline specifications include both static and transient limits.
2. This table is intended to aid in reading discrete points on Figure 3.
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor V
CC and VSS pins. Refer to
the Intel
®
Pentium
®
4 Processor VR-Down Design Guidelines for socket loadline guidelines and VR
implementation details.
Table 7. VCC Static and Transient Tolerance
Icc (A)
Voltage Deviation from VID Setting (V)
1, 2, 3
Maximum Typical Minimum
0 0.000 –0.025 –0.050
5 –0.010 –0.037 –0.064
10 –0.019 –0.048 –0.078
15 –0.029 –0.060 –0.092
20 –0.038 –0.072 –0.106
25 –0.048 –0.083 –0.120
30 –0.057 –0.095 –0.133
35 –0.067 –0.107 –0.147
40 –0.076 –0.119 –0.161
45 –0.085 –0.130 –0.175
50 –0.095 –0.142 –0.189
55 –0.105 –0.154 –0.203
60 –0.114 –0.165 –0.217
65 –0.124 –0.177 –0.231
70 –0.133 –0.189 –0.245