Intel Celeron Processor for the PGA370 Socket up to 1.40 GHz on 0.13 Micron Process Datasheet

Datasheet 3
Intel
®
Celeron
®
Processor for PGA370 up to 1.40 GHz on 0.13 µ Process
Contents
1.0 Introduction.........................................................................................................................9
1.1 Terminology.........................................................................................................10
1.1.1 Package and Processor Terminology ....................................................10
1.1.2 Processor Naming Convention...............................................................11
1.2 Related Documents.............................................................................................12
2.0 Electrical Specifications....................................................................................................13
2.1 Processor System Bus and V
REF .......................................................................................... 13
2.2 Clock Control and Low Power States..................................................................14
2.2.1 Normal State—State 1 ...........................................................................15
2.2.2 AutoHALT Powerdown State—State 2...................................................15
2.2.3 Stop-Grant State—State 3 .....................................................................15
2.2.4 HALT/Grant Snoop State—State 4 ........................................................15
2.2.5 Sleep State—State 5..............................................................................16
2.2.6 Deep Sleep State—State 6 ....................................................................16
2.2.7 Clock Control..........................................................................................17
2.3 Power and Ground Pins ......................................................................................17
2.3.1 Phase Lock Loop (PLL) Power...............................................................17
2.4 Decoupling Guidelines ........................................................................................18
2.4.1 Processor VCC
CORE
Decoupling............................................................18
2.5 Processor System Bus Clock and Processor Clocking .......................................19
2.6 Voltage Identification...........................................................................................19
2.7 Processor System Bus Unused Pins...................................................................21
2.8 Processor System Bus Signal Groups ................................................................22
2.8.1 Asynchronous vs. Synchronous for System Bus Signals.......................23
2.8.2 System Bus Frequency Select Signals ..................................................24
2.9 Test Access Port (TAP) Connection....................................................................25
2.10 Maximum Ratings................................................................................................25
2.11 Processor Voltage Level Specifications ..............................................................25
2.12 AGTL System Bus Specifications........................................................................30
2.13 System Bus Timing Specifications ......................................................................31
3.0 Signal Quality Specifications............................................................................................41
3.1 BCLK/BCLK# & PICCLK Signal Quality Specifications and
Measurement Guidelines ....................................................................................41
3.2 AGTL Signal Quality Specifications and Measurement Guidelines.....................42
3.2.1 Overshoot/Undershoot Guidelines .........................................................43
3.2.2 Overshoot/Undershoot Magnitude .........................................................44
3.2.3 Overshoot/Undershoot Pulse Duration...................................................44
3.2.4 Activity Factor.........................................................................................44
3.2.5 Reading Overshoot/Undershoot Specification Tables............................45
3.2.6 Determining if a System Meets the Overshoot/Undershoot
Specifications .........................................................................................46
3.3 Non-AGTL Signal Quality Specifications and Measurement Guidelines.............47
3.3.1 Overshoot/Undershoot Guidelines .........................................................48
3.3.2 Ringback Specification ...........................................................................48
3.3.3 Settling Limit Guideline...........................................................................49