Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
11
SUMMARY OF ERRATA
NO.
mcbA0 mcpA0
cmmA0 Plans ERRATA
H24 X X X NoFix Premature execution of a load operation prior to
exception handler invocation
H25 X X X NoFix Read portion of RMW instruction may execute twice
H26 X X X Fix Intervening writeback may occur during locked
transaction
H27 X X X NoFix MC2_STATUS MSR has model-specific error code
and machine check architecture error code reversed
H28 X X X NoFix Mixed cacheability of lock variables is problematic in
MP systems
H29 X Fix Thermal sensor may assert SMBALERT# incorrectly
H30 X X X NoFix MOV with debug register causes debug exception
H31 X X X NoFix Upper four PAT entries not usable with Mode B or
Mode C paging
H32 X X X Fix Incorrect memory type may be used when MTRRs
are disabled
H33 X X X Fix Misprediction in program flow may cause
unexpected instruction execution
H34 X X X NoFix Data breakpoint exception in a displacement relative
near call may corrupt eip
H35 X X X NoFix System bus ECC not functional with 2:1 ratio
H36 X X X Fix Fault on REP CMPS/SCAS operation may cause
incorrect EIP
H37 X X X NoFix RDMSR and WRMSR to invalid MSR address may
not cause GP fault
H38 X X X NoFix SYSENTER/SYSEXIT instructions can implicitly load
“null segment selector” to SS and CS registers
H39 X X X NoFix PRELOAD followed by EXTEST does not load
boundary scan data
H40 X X X NoFix Far jump to new TSS with D-bit cleared may cause
system hang
H41 X X X NoFix Incorrect chunk ordering may prevent execution of
the Machine Check Exception handler after BINIT#
H42 X X X NoFix Resume Flag may not be cleared after debug
exception
H43 X Fix Processor may return invalid parameters on
execution of the CPUID instruction
H44 X X X NoFix Internal cache protocol violation may cause system
hang
H45 X X X NoFix GP# fault on WSMSR to ROB_CR_BKUPTMPDR6