Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

38 Datasheet
Intel
®
Celeron
®
Processor in the 478-Pin Package
Figure 13. THERMTRIP# Power Down Sequenc e
Figure 14. Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform
Figure 15. TAP Valid Delay Timing Waveform
THERMTRIP#
Vcc
T39
T39 < 0.5 seconds
Note: THERMTRIP# is undefined when RESET# is active
T64 (TRST# Pulse Width), V=0.5*Vcc
V
T
q
T38 (PROCHOT# Pulse Width), V=GTLREF
=
Tq
Tx = T63 (Valid Time)
Ts = T61 (Setup Time)
Th = T62 (Hold Time)
V = 0.5 * V
CC
TCK
Signal
Tx Ts Th
V Valid
V