Specification Update

Errata
Specification Update 51
AM93. CPUID Incorrectly Reports Support for C2/C2E on Some Processors
Problem: CPUID.05H:EDX [bits 11-8] incorrectly reports support for C2/C2E C-state in the
number of C2 Sub C-states. A value of 02H is reported, where the correct value is
00H. The affected processors are identified by the following CPUID Brand Strings:
• Intel(R) Celeron(R) CPU 420 @ 1.60GHz
• Intel(R) Celeron(R) CPU 430 @ 1.80GHz
• Intel(R) Celeron(R) CPU 440 @ 2.00GHz
Implication: CPUID will incorrectly report support of C2/C2E when it is not supported. BIOS should
not attempt to enable this feature as these modes are not supported.
Workaround: Software should not rely on CPUID Sub C-States information on the affected
processors.
Status: For the steppings affected, see the Summary Tables of Changes.
AM94. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance
Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch Record
(LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag (bit 11) to 1 in
IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon the occurrence of a
hardware PMI request. Due to this erratum, the LBR freeze may occur too soon (i.e.
before the hardware PMI request).
Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date LBR
information that does not describe the last few branches before the PEBS sample that
triggered the PMI.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.