Specification Update

Errata
Specification Update 35
AM49 BTS Message May Be Lost When the STPCLK# Signal is Active.
Problem: STPCLK# is asserted to enable the processor to enter a low-power state. Under some
circumstances, when STPCLK# becomes active, the BTS (Branch Trace Store)
message may be either lost and not written or written with corrupted branch address
to the Debug Store area.
Implication: BTS messages may be lost or be corrupted in the presence of STPCLK# assertions.
Workaround: None Identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AM50 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 2
48
May Terminate Early
Problem: In 64-bit Mode CMPSB, LODSB, or SCASB executed with a repeat prefix and count
greater than or equal to 2
48
may terminate early. Early termination may result in one
of the following.
• The last iteration not being executed
• Signaling of a canonical limit fault (#GP) on the last iteration
Implication: While in 64-bit mode, with count greater or equal to 2
48
, repeat string operations
CMPSB, LODSB or SCASB may terminate without completing the last iteration. Intel
has not observed this erratum with any commercially available software.
Workaround: Do not use repeated string operations with RCX greater than or equal to 2
48
.
Status: For the steppings affected, see the Summary Tables of Changes.
AM51 REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page
Boundaries with Inconsistent Memory Types may use an Incorrect Data Size
or Lead to Memory-Ordering Violations.
Problem: Under certain conditions as described in the Software Developers Manual section “Out-
of-Order Stores For string operations in Pentium 4, Intel Xeon, and P6 Family
Processors” the processor performs REP MOVS or REP STOS as fast strings. Due to
this erratum fast string REP MOVS/REP STOS instructions that cross page boundaries
from WB/WC memory types to UC/WP/WT memory types, may start using an
incorrect data size or may observe memory ordering violations.
Implication: Upon crossing the page boundary the following may occur, dependent on the new
page memory type:
• UC the data size of each write will now always be 8 bytes, as opposed to the
original data size.
• WP the data size of each write will now always be 8 bytes, as opposed to the
original data size and there may be a memory ordering violation.
• WT there may be a memory ordering violation.
Workaround: Software should avoid crossing page boundaries from WB or WC memory type to UC,
WP or WT memory type within a single REP MOVS or REP STOS instruction that will
execute with fast strings enabled.
Status: For the steppings affected, see the Summary Tables of Changes.