Specification Update

Errata
Specification Update 31
AM37 PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is
Enabled
Problem: PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may not be
executed when Alignment Check is enabled.
Implication: PREFETCHh instructions may not perform the data prefetch if Alignment Check is
enabled.
Workaround: Clear the AC flag (bit 18) in the EFLAGS register and/or the AM bit (bit 18) of Control
Register CR0 to disable alignment checking.
Status: For the steppings affected, see the Summary Tables of Changes.
AM38 Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory
Image May Be Unexpectedly All 1's after FXSAVE
Problem: The upper 32 bits of the FPU Data (Operand) Pointer may incorrectly be set to all 1's
instead of the expected value of all 0's in the FXSAVE memory image if all of the
following conditions are true:
• The processor is in 64-bit mode.
• The last floating point operation was in compatibility mode
• Bit 31 of the FPU Data (Operand) Pointer is set.
• An FXSAVE instruction is executed
Implication: Software depending on the full FPU Data (Operand) Pointer may behave
unpredictably.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AM39 Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate
Problem: Performance monitoring events that count the number of cycles the divider is busy
and no other execution unit operation or load operation is in progress may not be
accurate.
Implication: The counter may reflect a value higher or lower than the actual number of events.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.