Specification Update

Errata

AT83. Storage of PEBS Record Delayed Following Execution of MOV SS or

STI

Problem: When a performance monitoring counter is configured for PEBS (Precise

Event Based Sampling), overflow of the counter results in storage of a PEBS

record in the PEBS buffer. The information in the PEBS record represents the

state of the next instruction to be executed following the counter overflow.

Due to this erratum, if the counter overflow occurs after execution of either

MOV SS or STI, storage of the PEBS record is delayed by one instruction.

Implication: When this erratum occurs, software may observe storage of the PEBS record

being delayed by one instruction following execution of MOV SS or STI. The

state information in the PEBS record will also reflect the one instruction delay.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AT84. Store Ordering May be Incorrect between WC and WP Memory Types

Problem: According to Intel® 64 and IA-32 Intel Architecture Software Developer's

Manual, Volume 3A "Methods of Caching Available", WP (Write Protected)

stores should drain the WC (Write Combining) buffers in the same way as UC

(Uncacheable) memory type stores do. Due to this erratum, WP stores may

not drain the WC buffers.

Implication: Memory ordering may be violated between WC and WP stores.

Workaround: None identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AT85. Fixed Function Performance Counters MSR_PERF_FIXED_CTR1

(30AH) and MSR_PERF_FIXED_CTR2 (30BH) are Not Cleared When

the Processor is Reset

Problem: The Fixed Function Performance Counters that count the number of core

cycles and reference cycles when the core is not in a halt state are not

cleared when the processor is reset.

Implication: The MSR_PERF_FIXED_CTR1 and MSR_PERF_FIXED_CTR2 counters may

contain unexpected values after reset.

Workaround: BIOS can workaround this erratum by clearing the counters at processor

initialization time.

Status: For the steppings affected, see the Summary Tables of Changes.