Uncore Manual

Reference Number: 329468-002 17
Uncore Performance Monitoring
Uncore Per-Socket Performance Monitoring Control
Monitoring:
e) Select how to gather data. If polling, skip to f. If sampling:
To set up a sample interval, software can pre-program the data register with a value of [2^(register
bit width - up to 48) - sample interval length]. Doing so allows software, through use of the pmi
mechanism, to be notified when the number of events in the sample have been captured. Capturing
a performance monitoring sample every ‘X cycles’ (the fixed counter in the UBox counts uncore clock
cycles) is a common use of this mechanism.
i.e. To stop counting and receive notification when the 1,000,000th idle flit is transmitted from QPI on
Port 0
- set Q_P0_PCI_PMON_CTR1 to (2^48- 1000)
- set Q_P0_PCI_PMON_CTL1.ev_sel to 0x0
- set Q_P0_PCI_PMON_CTL1.umask to 0x1
- set U_MSR_PMON_GLOBAL_CTL.pmi_core_sel to which core the monitoring thread is executing on.
f) Enable counting at the global level by setting the U_MSR_PMON_GLOBAL_CTL.unfrz_all bit to 1.
OR
f) Enable counting at the box level by unfreezing the counters in each box
e.g. set Cn_MSR_PMON_BOX_CTL.frz to 0
And with that, counting will begin.
NOTE
The UBox does not have a Box Control register, so there’s no box-level freeze to help
isolate the UBox from agents counting in other boxes. Once enabled and programmed
with a valid event, the UBox counters will collect events. For somewhat better
synchronization, a user can keep the U_MSR_PMON_CTL.ev_sel at 0x0 while enabled
and write it with a valid value just prior to unfreezing the registers in other boxes.
2.1.3 Reading the Sample Interval
Software can poll the counters whenever it chooses, or wait to be notified that a counter has over-
flowed (by receiving a PMI).
a) Polling - before reading, it is recommended that software freeze the counters in each box with
active counters (by setting *_PMON_BOX_CTL.frz to 1). After reading the event counts from the
counter registers, the monitoring agent can choose to reset the event counts to avoid event-count
wrap-around; or resume the counter register without resetting their values. The latter choice will
require the monitoring agent to check and adjust for potential wrap-around situations.
b) Frozen counters - If software set the counters to freeze on overflow and send notification when it
happens, the next question is: Who caused the freeze?
Overflow bits are stored hierarchically within the uncore. First, software should read the
U_MSR_PMON_GLOBAL_STATUS.ov_* bits to determine which box(es) sent an overflow. Then read
that box’s *_PMON_GLOBAL_STATUS.ov field to find the overflowing counter.
NOTE
More than one counter may overflow at any given time.