Intel Celeron Processor on 0.13 Micron Process in the 478-Pin Package Datasheet

Intel
®
Celeron
®
Processor on 0.13 Micron Process in the 478-Pin Package Datasheet 85
Features
Features 7
7.1 Power-On Configuration Options
Several configuration options can be configured by hardware. Celeron processor on 0.13 micron
process sample their hardware configuration at reset, on the active-to-inactive transition of
RESET#. For specifications on these options, refer to Table 38.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor. For reset
purposes, the processor does not distinguish between a “warm” reset and a “power-on” reset.
7.2 Clock Control and Low Power States
The use of AutoHALT, Stop-Grant, and Sleep states is allowed in Celeron processor on
0.13 micron process based systems to reduce power consumption by stopping the clock to internal
sections of the processor, depending on each particular state. See Figure 37 for a visual
representation of the processor low power states.
7.2.1 Normal State—State 1
This is the normal operating state for the processor.
Table 38. Power-On Configuration Option Pins
Configuration Option Pin
1
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
Output tristate SMI#
Execute BIST INIT#
In Order Queue pipelining (set IOQ depth to 1) A7#
Disable MCERR# observation A9#
Disable BINIT# observation A10#
APIC Cluster ID (0-3) A[12:11]#
Disable bus parking A15#
Symmetric agent arbitration ID BR0#