Specification Update

MOBILE INTEL

CELERON

PROCESSOR at 466 MHz, 433 MHz, 400 MHz,

366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE

H2. Differences Exist in Debug Exception Reporting

Problem: There exist some differences in the reporting of code and data breakpoint matches between that

specified by previous Intel processors’ specifications and the behavior of the Mobile Intel® Celeron® processor,

as described below:

Case 1: The first case is for a breakpoint set on a MOVSS or POPSS instruction, when the instruction following

it causes a debug register protection fault (DR7.gd is already set, enabling the fault). The processor reports

delayed data breakpoint matches from the MOVSS or POPSS instructions by setting the matching DR6.bi bits,

along with the debug register protection fault (DR6.bd). If additional breakpoint faults are matched during the

call of the debug fault handler, the processor sets the breakpoint match bits (DR6.bi) to reflect the breakpoints

matched by both the MOVSS or POPSS breakpoint and the debug fault handler call. The Mobile Intel®

Celeron® processor only sets DR6.bd in either situation, and does not set any of the DR6.bi bits.

Case 2: In the second breakpoint reporting failure case, if a MOVSS or POPSS instruction with a data

breakpoint is followed by a store to memory which:

a) crosses a 4-Kbyte page boundary,

b) causes the page table Access or Dirty (A/D) bits to be modified,

the breakpoint information for the MOVSS or POPSS will be lost. Previous processors retain this information

under these boundary conditions.

Case 3: If they occur after a MOVSS or POPSS instruction, the INTn, INTO, and INT3 instructions zero the

DR6.bi bits (bits B0 through B3), clearing pending breakpoint information, unlike previous processors.

Case 4: If a data breakpoint and an SMI (System Management Interrupt) occur simultaneously, the SMI will be

serviced via a call to the SMM handler, and the pending breakpoint will be lost.

Case 5: When an instruction which accesses a debug register is executed, and a breakpoint is encountered on

the instruction, the breakpoint is reported twice.

Case 6: Unlike previous versions of Intel Architecture processors, Mobile Intel® Celeron® processors will not

set the Bi bits for a matching disabled breakpoint unless at least one other breakpoint is enabled.

Implication: When debugging or when developing debuggers for a Mobile Intel® Celeron® processor-based

system, this behavior should be noted. Normal usage of the MOVSS or POPSS instructions (i.e., following them

with a MOV ESP) will not exhibit the behavior of cases 1-3. Debugging in conjunction with SMM will be limited

by case 4.

Workaround: Following MOVSS and POPSS instructions with a MOV ESP instruction when using

breakpoints will avoid the first three cases of this erratum. No workaround has been identified for cases 4, 5, or

Status: For the steppings affected see the Summary of Changes at the beginning of this section.