Specification Update

Errata
50 Specification Update
AT91. PMI While LBR Freeze Enabled May Result in Old/Out-of-date LBR
Information
Problem: When Precise Event-Based Sampling (PEBS) is configured with Performance
Monitoring Interrupt (PMI) on PEBS buffer overflow enabled and Last Branch
Record (LBR) Freeze on PMI enabled by setting FREEZE_LBRS_ON_PMI flag
(bit 11) to 1 in IA32_DEBUGCTL (MSR 1D9H), the LBR stack is frozen upon
the occurrence of a hardware PMI request. Due to this erratum, the LBR
freeze may occur too soon (i.e. before the hardware PMI request).
Implication: Following a PMI occurrence, the PMI handler may observe old/out-of-date
LBR information that does not describe the last few branches before the PEBS
sample that triggered the PMI.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AT92. A Memory Access May Get a Wrong Memory Type Following a #GP
due to WRMSR to an MTRR Mask
Problem: The TLB (Translation Lookaside Buffer) may indicate a wrong memory type
on a memory access to a large page (2M/4M Byte) following the recovery
from a #GP (General Protection Fault) due to a WRMSR to one of the
IA32_MTRR_PHYSMASKn MSRs with reserved bits set.
Implication: When this erratum occurs, a memory access may get an incorrect memory
type leading to unexpected system operation. As an example, an access to a
memory mapped I/O device may be incorrectly marked as cacheable, become
cached, and never make it to the I/O device. Intel has not observed this
erratum with any commercially available software.
Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn
MSRs.
Status: For the steppings affected, see the Summary Tables of Changes.
AT93. RSM Instruction Execution under Certain Conditions May Cause
Processor Hand or Unexpected Instruction Execution Results
Problem: RSM instruction execution, under certain conditions triggered by a complex
sequence of internal processor micro-architectural events, may lead to
processor hang, or unexpected instruction execution results.
Implication: In the above sequence, the processor may live lock or hang, or RSM
instruction may restart the interrupted processor context through a
nondeterministic EIP offset in the code segment, resulting in unexpected
instruction execution, unexpected exceptions or system hang. Intel has not
observed this erratum with any commercially available software.