Specification Update

Errata

AT40. SYSCALL Immediately after Changing EFLAGS.TF May Not Behave

According to the New EFLAGS.TF

Problem:

If a SYSCALL instruction follows immediately after EFLAGS.TF was updated and

IA32_FMASK.TF (bit 8) is cleared, then under certain circumstances SYSCALL may

behave according to the previous EFLAGS.TF.

Implication: When the problem occurs, SYSCALL may generate an unexpected debug exception, or

may skip an expected debug exception.

Workaround: Mask EFLAGS.TF by setting IA32_FMASK.TF (bit 8).

Status: For the steppings affected, see the Summary Tables of Changes.

AT41. Code Segment Limit/Canonical Faults on RSM May be Serviced before

Higher Priority Interrupts/Exceptions

Problem:

Normally, when the processor encounters a Segment Limit or Canonical Fault due to

code execution, a #GP (General Protection Exception) fault is generated after all

higher priority Interrupts and exceptions are serviced. Due to this erratum, if RSM

(Resume from System Management Mode) returns to execution flow that results in a

Code Segment Limit or Canonical Fault, the #GP fault may be serviced before a higher

priority Interrupt or Exception (e.g. NMI (Non-Maskable Interrupt), Debug break

(#DB), Machine Check (#MC), etc.)

Implication: Operating systems may observe a #GP fault being serviced before higher priority

Interrupts and Exceptions. Intel has not observed this erratum on any commercially

available software.

Workaround: None Identified.

Status: For the steppings affected, see the Summary Tables of Changes.

AT42. IA32_FMASK is Reset during an INIT

Problem:

IA32_FMASK MSR (0xC0000084) is reset during INIT.

Implication: If an INIT takes place after IA32_FMASK is programmed, the processor will overwrite

the value back to the default value.

Workaround: Operating system software should initialize IA32_FMASK after INIT.

Status: For the steppings affected, see the Summary Tables of Changes.