Intel Celeron Processor in the 478-Pin Package at 1.80 GHz Datasheet

Datasheet 35
Intel
®
Celeron
®
Processor in the 478-Pin Package
Figure 8. System Bus Common Clock Valid Delay Timings
BCLK0
BCLK1
Common Clock
Signal (@ driver)
Common Clock
Signal (@ receiver)
T0
T1 T2
T
Q
T
R
valid valid
valid
T
P
T
P
= T10: T
CO
(Data Valid Output Delay)
T
Q
= T11: T
SU
(Common Clock Setup)
T
R
= T12: T
H
(Common Clock Hold Time)
Figure 9. System Bus Reset and Configuration Timings
BCLK
RESET#
Configuration
(A[31:3], BR0#,
INIT#, SMI#)
Tv
Tw Tx
Tv = T13 (RESET# Pulse Width)
Tw = T45 (Reset Configuration Signals Setup Time)
Tx = T46 (Reset Configuration Signals Hold Time)