Specification Update

Errata
52 Specification Update
AM95. A Memory Access May Get a Wrong Memory Type Following a #GP due to
WRMSR to an MTRR Mask
Problem: The TLB (Translation Lookaside Buffer) may indicate a wrong memory type on a
memory access to a large page (2M/4M Byte) following the recovery from a #GP
(General Protection Fault) due to a WRMSR to one of the IA32_MTRR_PHYSMASKn
MSRs with reserved bits set.
Implication: When this erratum occurs, a memory access may get an incorrect memory type
leading to unexpected system operation. As an example, an access to a memory
mapped I/O device may be incorrectly marked as cacheable, become cached, and
never make it to the I/O device. Intel has not observed this erratum with any
commercially available software.
Workaround: Software should not attempt to set reserved bits of IA32_MTRR_PHYSMASKn MSRs.
Status: For the steppings affected, see the Summary Tables of Changes.
AM96. Performance Monitoring Event FP_MMX_TRANS_TO_MMX May Not Count
Some Transitions
Problem: Performance Monitor Event FP_MMX_TRANS_TO_MMX (Event CCH, Umask 01H)
counts transitions from x87 Floating Point (FP) to MMX™ instructions. Due to this
erratum, if only a small number of MMX instructions (including EMMS) are executed
immediately after the last FP instruction, a FP to MMX transition may not be counted.
Implication: The count value for Performance Monitoring Event FP_MMX_TRANS_TO_MMX may be
lower than expected. The degree of undercounting is dependent on the occurrences of
the erratum condition while the counter is active. Intel has not observed this erratum
with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.