Specification Update

Errata
30 Specification Update
AM35 FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and
Cause a Wrap to a Misaligned Base Address (Alignment <= 0x10h) May Cause
FPU Instruction or Operand Pointer Corruption
Problem: If a FXSAVE/FXRSTOR instruction stores to the end of the segment causing a wrap to
a misaligned base address (alignment <= 0x10h), and one of the following conditions
is satisfied:
1. 32-bit addressing, obtained by using address-size override, when in 64-bit mode.
2. 16-bit addressing in legacy or compatibility mode.
Then, depending on the wrap-around point, one of the below saved values may be
corrupted:
• FPU Instruction Pointer Offset
• FPU Instruction Pointer Selector
• FPU Operand Pointer Selector
• FPU Operand Pointer Offset
Implication: This erratum could cause FPU Instruction or Operand pointer corruption and may lead
to unexpected operations in the floating point exception handler.
Workaround: Avoid segment base mis-alignment and address wrap-around at the segment
boundary.
Status: For the steppings affected, see the Summary Tables of Changes.
AM36 PREFETCHh Instruction Execution under Some Conditions May Lead to
Processor Livelock
Problem: PREFETCHh instruction execution after a split load and dependent upon ongoing store
operations may lead to processor livelock.
Implication: Due to this erratum, the processor may livelock.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.