Specification Update
Summary Tables of Changes
Specification Update 11
NO A1 Plan ERRATA
AM38 X Plan Fix
Upper 32 Bits of the FPU Data (Operand) Pointer in the FXSAVE Memory Image May
Be Unexpectedly All 1's after FXSAVE
AM39 X Plan Fix Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate
AM40 X No Fix Values for LBR/BTS/BTM will be Incorrect after an Exit from SMM
AM41 X Plan Fix
SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to the
New EFLAGS.TF
AM42 X No Fix
Code Segment Limit/Canonical Faults on RSM May be Serviced before Higher Priority
Interrupts/Exceptions and May Push the Wrong Address Onto the Stack
AM43 X Plan Fix IA32_FMASK is Reset during an INIT
AM44 X No Fix
An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/POP
SS Instruction if it is Followed by an Instruction That Signals a Floating Point
Exception
AM45 X No Fix Last Branch Records (LBR) Updates May be Incorrect after a Task Switch
AM46 X No Fix IO_SMI Indication in SMRAM State Save Area May Be Set Incorrectly
AM47 X No Fix INIT Does Not Clear Global Entries in the TLB
AM48 X Plan Fix
Using Memory Type Aliasing with Memory Types WB/WT May Lead to Unpredictable
Behavior
AM49 X Plan Fix BTS Message May Be Lost When the STPCLK# Signal is Active
AM50 X No Fix
CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to 2
48
May
Terminate Early
AM51 X No Fix
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries
with Inconsistent Memory Types may use an Incorrect Data Size or Lead to Memory-
Ordering Violations.
AM52 X No Fix MOV To/From Debug Registers Causes Debug Exception
AM53 X No Fix
LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in
64-bit Mode
AM54 X No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid
AM55 X No Fix
Returning to Real Mode from SMM with EFLAGS.VM Set May Result in Unpredictable
System Behavior
AM56 X No Fix IRET under Certain Conditions May Cause an Unexpected Alignment Check Exception
AM57 X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AM58 X Plan Fix CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address
AM59 X Plan Fix PEBS Does Not Always Differentiate Between CPL-Qualified Events
AM60 X No Fix PMI May Be Delayed to Next PEBS Event
AM61 X Plan Fix
PEBS Buffer Overflow Status Will Not be Indicated Unless IA32_DEBUGCTL[12] is
Set
AM62 X No Fix Asynchronous MCE During a Far Transfer May Corrupt ESP
AM63 X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code Breakpoint
AM64 X No Fix BTM/BTS Branch-From Instruction Address May be Incorrect for Software Interrupts