Guide

System Overview

Intel

852GM Chipset Platform Design Guide 23

• The execution trace cache is a first level cache that stores approximately 12-k decoded micro-

operations, which removes the decoder from the main execution path.

2.2.2. Mobile Intel Pentium 4 Processor-M

The processor utilizes flip-chip pin grid array (FC-PGA2) package technology, which plugs into a 478-

pin surface mount, zero insertion force (ZIF) socket, referred to as the mPGA478B socket.

Processor features include:

• On-die 512-kB second level cache

• Hyper pipelined technology

• 400-MHz Front Side Bus quad-pumped bus running off a 100-MHz system clock making 3.2

GB/sec data transfer rates possible

• Supports Streaming SIMD Extensions 2 (SSE2)

• Enhanced Intel

SpeedStep

technology which enables real-time dynamic switching of the voltage

and frequency between two performance modes.

• 35-W thermal design power

2.2.3. Intel Celeron M Processor

The Intel Celeron M processor utilizes stocketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and

surface mount Micro Flip-Chip Ball Grid Array(Micro-FCBGA) package technology. The Micro-

FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is

referred to as the mPGA479M socket.

Processor features include:

• On-die primary 32-kB, instruction cache and 32-kbyte, write-back data cache

• On-die 512-kB second level cache

• Supports Streaming SIMD Extensions 2 (SSE2)

• Advanced Gunning Transceiver Logic (AGTL+) bus driver technology

• Supports host bus dynamic bus inversion (DINV)

• Dynamic power down of Data Bus buffers

• BPRI# control to Disable Address/Control buffers

• Package/Power

⎯ Micro-FCPGA and 479-ball Micro-FCBGA packages

⎯ VCC-CORE: Offered in 1.356 V standard voltage and 1.004 V ultra low voltage cores

⎯ VCCA (1.8 V)

⎯ VCCP (1.05 V)

The following list provides some of the key enhancement features on this processor:

• Supports Intel Architecture with Dynamic Execution