Guide

System Memory Design Guidelines (DDR-SDRAM)
R
Intel
®
852GM Chipset Platform Design Guide 123
3. It is possible to route using 2 vias if one via is shared that connects to the SO-DIMM pad and parallel
termination resistor.
4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
7.3.7.3. CPC to Clock Length Matching Requirements
The total length of the CPC signals, between the GMCH die pad and the SO-DIMM must fall within the
range defined below, with respect to the associated clock reference length. Refer to Figure 60 for a
definition of the various trace segments. The length the trace from the SO-DIMM to the termination
resistor need not be length matched. The length matching requirements are also depicted in Figure 61.
Refer to Section 7.1 for more details on length matching requirements. A table of CPC signal package
length is provided in Section 7.3.7.4.
Length range formula for SO-DIMM0:
X
0
= SCK/SCLK#[1:0] total reference length, including package length. See clock 7.3.1
Y
0
= SMA[5,4,2,1] total length = GMCH package + L1, as shown in Figure 60,
where: ( X
0
– 1.0” ) ≤ Y
0
≤ ( X
0
+ 0.5” )
Length range formula for SO-DIMM1:
X
1
= SCK/SCLK#[4:3] total reference length, including package length. See clock 7.3.1.
Y
1
= SMAB[5,4,2,1] total length = GMCH package + L1, as shown in Figure 60,
where: ( X
1
– 1.0” ) ≤ Y
1
≤ ( X
1
+ 0.5” )
No length matching is required from SO-DIMM1 to the termination resistor. Figure 61 on the following
page depicts the length matching requirements between the CPC signals and clock. A nominal CPC
package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 7.2 for more
details on package length compensation.