Specification Update

Specification Clarifications

Specification Clarifications

The Specification Clarifications listed in this section apply to the following documents:

• Intel

Celeron

Processor 200 Sequence Datasheet

• Intel

64 and IA-32 Architectures Software Developer’s Manual volumes 1,2A, 2B,

3A, and 3B

All Specification Clarifications will be incorporated into a future version of the

appropriate Intel

Celeron

processor 200 sequence documentation.

AT1. Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS)

Invalidation

Section 10.9 INVALIDATING THE TRANSLATION LOOKASIDE BUFFERS (TLBS)

of the Intel® 64 and IA-32 Architectures Software Developer's Manual,

Volume 3A: System Programming Guide will be modified to include the

presence of page table structure caches, such as the page directory cache,

which Intel processors implement. This information is needed to aid

operating systems in managing page table structure invalidations properly.

Intel will update the Intel® 64 and IA-32 Architectures Software Developer's

Manual, Volume 3A: System Programming Guide in the coming months. Until

that time, an application note, TLBs, Paging-Structure Caches, and Their

Invalidation (FDBL > Home > Software Development > Software Dev Info >

IA32/Pentium III), is available which provides more information on the

paging structure caches and TLB invalidation.

In rare instances, improper TLB invalidation may result in unpredictable

system behavior, such as system hangs or incorrect data. Developers of

operating systems should take this documentation into account when

designing TLB invalidation algorithms. For the processors affected, Intel has

provided a recommended update to system and BIOS vendors to incorporate

into their BIOS to resolve this issue.