Specification Update

Errata
Specification Update 49
AM88 Updating Code Page Directory Attributes without TLB Invalidation May Result
in Improper Handling of Code #PF
Problem: Code #PF (Page Fault exception) is normally handled in lower priority order relative to
both code #DB (Debug Exception) and code Segment Limit Violation #GP (General
Protection Fault). Due to this erratum, code #PF may be handled incorrectly, if all of
the following conditions are met:
• A PDE (Page Directory Entry) is modified without invalidating the corresponding
TLB (Translation Look-aside Buffer) entry
• Code execution transitions to a different code page such that both
⎯ The target linear address corresponds to the modified PDE
⎯ The PTE (Page Table Entry) for the target linear address has an A (Accessed)
bit that is clear
• One of the following simultaneous exception conditions is present following the
code transition
⎯ Code #DB and code #PF
⎯ Code Segment Limit Violation #GP and code #PF
Implication: Software may observe either incorrect processing of code #PF before code Segment
Limit Violation #GP or processing of code #PF in lieu of code #DB.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AM89 Performance Monitoring Event BR_INST_RETIRED May Count CPUID
Instructions as Branches
Problem: Performance monitoring event BR_INST_RETIRED (C4H) counts retired branch
instructions. Due to this erratum, two of its sub-events mistakenly count for CPUID
instructions as well. Those sub events are: BR_INST_RETIRED.PRED_NOT_TAKEN
(Umask 01H) and BR_INST_RETIRED.ANY (Umask 00H).
Implication: The count value returned by the performance monitoring event
BR_INST_RETIRED.PRED_NOT_TAKEN or BR_INST_RETIRED.ANY may be higher than
expected. The extent of over counting depends on the occurrence of CPUID
instructions, while the counter is active.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.