Guide

R
Intel
®
852GM Chipset Platform Design Guide 15
Table 47. CPC Group Package Lengths ............................................................................... 125
Table 48. Recommended GMCH RAMDAC Components.................................................... 133
Table 49. Signal Group and Signal Pair Names ................................................................... 135
Table 50. LVDS Signal Trace Length Matching Requirements ............................................ 135
Table 51. LVDS Signal Group Routing Guidelines ............................................................... 136
Table 52. LVDS Package Lengths ........................................................................................ 137
Table 53. DVO Interface Trace Length Mismatch Requirements ......................................... 139
Table 54. DVOC Routing Guideline Summary...................................................................... 140
Table 55. DVOC Interface Package Lengths ........................................................................ 141
Table 56. GMBUS Pair Mapping and Options....................................................................... 142
Table 57. Hub Interface RCOMP Resistor Values ................................................................ 145
Table 58. Hub Interface Signals Internal Layer Routing Summary....................................... 146
Table 59. Hub Interface Package Lengths for ICH4-M ......................................................... 147
Table 60. Hub Interface Package Lengths for GMCH........................................................... 147
Table 61. Hub Interface VREF/VSWING Reference Voltage Specifications ........................ 148
Table 62. Recommended Resistor Values for Single VREF/VSWING Divider Circuit ......... 149
Table 63. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for
ICH4-M................................................................................................................... 151
Table 64. Recommended Resistor Values for HLVREF and PSWING Divider Circuits for
GMCH .................................................................................................................... 152
Table 65. AC’97 AC_BIT_CLK Routing Summary ................................................................ 160
Table 66. AC’97 AC_SDOUT/AC_SYNC Routing Summary ................................................ 161
Table 67. AC’97 AC_SDIN Routing Summary ...................................................................... 161
Table 68. Supported Codec Configurations .......................................................................... 163
Table 69. USBRBIAS/USBRBIAS# Routing Summary ......................................................... 166
Table 70. USB 2.0 Trace Length Preliminary Guidelines (with Common Mode Choke) ...... 166
Table 71. Bus Capacitance Reference Chart........................................................................ 173
Table 72. Bus Capacitance/Pull-Up Resistor Relationship ................................................... 173
Table 73. RTC Routing Summary ......................................................................................... 177
Table 74. LAN Component Connections/Features ............................................................... 181
Table 75. LAN Design Guide Section Reference.................................................................. 181
Table 76. LAN LOM Routing Summary................................................................................. 183
Table 77. Intel 82562ET/EM Control Signals ........................................................................ 188
Table 78. Individual Clock Breakdown .................................................................................. 197
Table 79. Host Clock Group Routing Constraints ................................................................. 200
Table 80. Clock Package Length .......................................................................................... 201
Table 81. CLK66 Clock Group Routing Constraints.............................................................. 202
Table 82. CLK33 Clock Group Routing Constraints.............................................................. 203
Table 83. PCICLK Clock Group Routing Constraints............................................................ 204
Table 84. CLK14 Clock Group Routing Constraints.............................................................. 205
Table 85. DOTCLK Clock Routing Constraints ..................................................................... 206
Table 86. SSCCLK Clock Routing Constraints ..................................................................... 207
Table 87. USBCLK Clock Routing Constraints ..................................................................... 208
Table 88. Power Delivery Definitions .................................................................................... 211
Table 89. Power Management States on Intel Reference Board.......................................... 214
Table 90. Power Supply Rail Descriptions on Intel Reference Board................................... 214
Table 91. Timing Sequence Parameters for Figure 118 ....................................................... 218
Table 92. DDR Power-Up Initialization Sequence ................................................................ 220
Table 93. GMCH Decoupling Recommendations ................................................................. 222
Table 94. Analog Supply Filter Requirements....................................................................... 230
Table 95. ICH4-M Decoupling Requirements ....................................................................... 231
Table 96. Processor “Intel Reserved” Signal Pin-Map Locations ......................................... 233
Table 97. Intel 852GM RSVD and NC Signal Pin-Map Locations ........................................ 234
Table 98. Mobile Intel Pentium 4 Processor-M Power-up Timing Specifications ................. 243