Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
12
SUMMARY OF ERRATA
NO.
mcbA0 mcpA0
cmmA0 Plans ERRATA
H46 X X X NoFix Machine check exception may occur due to improper
line eviction in the IFU
H47 X X X NoFix Lower Bits of SMRAM SMBASE Register Cannot Be
Written With an ITP
H48 X X X NoFix Task switch may cause wrong PTE and PDE access
bit to be set
H49 X X X NoFix Unsynchronized cross-modifying code operations
can cause unexpected instruction execution results
H50 X X X NoFix Deadlock may occur due to illegal-instruction/page-
miss combination
H51 X X X NoFix FLUSH# assertion following STPCLK# may prevent
CPU clocks from stopping
H52 X X X NoFix Floating-point exception condition may be deferred
H53 X NoFix Race conditions may exist on thermal sensor SMBus
collision detection/arbitration circuitry
H54 X X X NoFix Intermittent power-on failure due to
uninitialized processor internal nodes
H55 X X X NoFix Selector for the LTR/LLDT register may get
corrupted
H56 X X X NoFix INIT does not clear global entries in the TLB
H57 X X X NoFix VM bit will be cleared on a double fault handler
H58 X X X NoFix Memory aliasing with inconsistent A and D bits may
cause processor deadlock
H59 X X X NoFix Use of memory aliasing with inconsistent memory
type may cause system hang
H60 X X X NoFix Processor may report invalid TSS fault instead of
Double fault during mode C paging
H61 X X X NoFix Machine check exception may occur when
interleaving code between different memory types
H62 X X X NoFix Wrong ESP Register Values During a Fault in VM86
Mode
H63 X X X NoFix APIC ICR Write May Cause Interrupt Not to be Sent
When ICR Delivery Bit Pending
H64 X X X NoFix Processor Incorrectly Samples NMI Interrupt after
RESET# Deassertion When Processor APIC is
Hardware-Disabled
H65 X X X NoFix The Instruction Fetch Unit (IFU) May Fetch
Instructions Based Upon Stale CR3 Data After a
Write to CR3 Register