Specification Update

MOBILE INTEL
®
CELERON
®
PROCESSOR at 466 MHz, 433 MHz, 400 MHz,
366 MHz, 333 MHz, 300 MHz, 266 MHz SPECIFICATION UPDATE
16
H3. Code Fetch Matching Disabled Debug Register May Cause
Debug Exception
Problem: The bits L0-3 and G0-3 enable breakpoints local to a task and global to all tasks, respectively. If one
of these bits is set, a breakpoint is enabled, corresponding to the addresses in the debug registers DR0 - DR3.
If at least one of these breakpoints is enabled, any of these registers are disabled (e.g., Ln and Gn are 0), and
RWn for the disabled register is 00 (indicating a breakpoint on instruction execution), normally an instruction
fetch will not cause an instruction-breakpoint fault based on a match with the address in the disabled register(s).
However, if the address in a disabled register matches the address of a code fetch which also results in a page
fault, an instruction-breakpoint fault will occur.
Implication:
While debugging software, extraneous instruction-breakpoint faults may be encountered if
breakpoint registers are not cleared when they are disabled. Debug software which does not implement a code
breakpoint handler will fail, if this occurs. If a handler is present, the fault will be serviced. Mixing data and code
may exacerbate this problem by allowing disabled data breakpoint registers to break on an instruction fetch.
Workaround: The debug handler should clear breakpoint registers before they become disabled.
Status: For the steppings affected see the Summary of Changes at the
beginning of this section.
H4. Double ECC Error on Read May Result in BINIT#
Problem: For this erratum to occur, the following conditions must be met:
• Machine Check Exceptions (MCEs) must be enabled.
• A dataless transaction (such as a write invalidate) must be occurring simultaneously with a transaction
which returns data (a normal read).
• The read data must contain a double-bit uncorrectable ECC error.
If these conditions are met, the Mobile Intel Celeron processor will not be able to determine which transaction
was erroneous, and instead of generating an MCE, it will generate a BINIT#.
Implication:
The bus will be reinitialized in this case. However, since a double-bit uncorrectable ECC error
occurred on the read, the MCE handler (which is normally reached on a double-bit uncorrectable ECC error for
a read) would most likely cause the same BINIT# event.
Workaround: Though the ability to drive BINIT# can be disabled in the Mobile Intel Celeron processor, which
would prevent the effects of this erratum, overall system behavior would not improve, since the error which
would normally cause a BINIT# would instead cause the machine to shut down. No other workaround has been
identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this section.