Data Sheet

Datasheet, Volume 1 of 2 95
Thermal Management
point. When a package DTS indicates that it has reached the TCC activation (a reading
of 0x0, except when the TCC activation offset is changed), the TCC will activate and
indicate an Adaptive Thermal Monitor event. A TCC activation will lower both processor
IA core and graphics core frequency, voltage, or both. Changes to the temperature can
be detected using two programmable thresholds located in the processor thermal
MSRs. These thresholds have the capability of generating interrupts using the
processor IA core's local APIC. Refer to the Intel 64 and IA-32 Architectures Software
Developer’s Manual for specific register and programming details.
5.1.5.2.1 Digital Thermal Sensor Accuracy (Taccuracy)
The error associated with DTS measurements will not exceed ±5 °C within the entire
operating range.
5.1.5.2.2 Fan Speed Control with Digital Thermal Sensor
Digital Thermal Sensor based fan speed control (T
FAN
) is a recommended feature to
achieve optimal thermal performance. At the T
FAN
temperature, Intel recommends full
cooling capability before the DTS reading reaches Tj
MAX
.
5.1.5.3 PROCHOT# Signal
PROCHOT# (processor hot) is asserted by the processor when the TCC is active. Only a
single PROCHOT# pin exists at a package level. When any DTS temperature reaches
the TCC activation temperature, the PROCHOT# signal will be asserted. PROCHOT#
assertion policies are independent of Adaptive Thermal Monitor enabling.
5.1.5.4 Bi-Directional PROCHOT#
By default, the PROCHOT# signal is set to input only. When configured as an input or
bi-directional signal, PROCHOT# can be used for thermally protecting other platform
components should they overheat as well. When PROCHOT# is driven by an external
device:
• The package will immediately transition to the lowest P-State (Pn) supported by the
processor IA cores and graphics cores. This is contrary to the internally-generated
Adaptive Thermal Monitor response.
• Clock modulation is not activated.
The processor package will remain at the lowest supported P-state until the system de-
asserts PROCHOT#. The processor can be configured to generate an interrupt upon
assertion and de-assertion of the PROCHOT# signal. Refer to the appropriate processor
family BIOS Specification (Refer Related Documents section) for specific register and
programming details.
When PROCHOT# is configured as a bi-directional signal and PROCHOT# is asserted by
the processor, it is impossible for the processor to detect a system assertion of
PROCHOT#. The system assertion will have to wait until the processor de-asserts
PROCHOT# before PROCHOT# action can occur due to the system assertion. While the
processor is hot and asserting PROCHOT#, the power is reduced but the reduction rate
is slower than the system PROCHOT# response of < 100 us. The processor thermal
control is staged in smaller increments over many milliseconds. This may cause several
milliseconds of delay to a system assertion of PROCHOT# while the output function is
asserted.