Data Sheet

Power Management
70 Datasheet, Volume 1 of 2
Note: Package C-states above C10 are not supported in S-Processor Line paired with Intel
®
200 Series Chipset Families Platform Controller Hub.
Table 4-2. Processor IA Core / Package State Support
State Description
C0 Active mode, processor executing code.
C1 AutoHALT processor IA core state (package C0 state).
C1E AutoHALT processor IA core state with lowest frequency and voltage operating point
(package C0 state).
C2 All processor IA cores in C3 or deeper. Memory path open. Temporary state before Package
C3 or deeper.
C3 Processor IA execution cores in C3 or deeper, flush their L1 instruction cache, L1 data cache,
and L2 cache to the LLC shared cache. LLC may be flushed. Clocks are shut off to each core.
C6 Processor IA execution cores in this state save their architectural state before removing core
voltage. BCLK is off.
C7 Processor IA execution cores in this state behave similarly to the C6 state. If all execution
cores request C7, LLC ways may be flushed until it is cleared. If the entire LLC is flushed,
voltage will be removed from the LLC.
C8 C7 plus LLC should be flushed.
C9 C8 plus most Uncore voltages at 0V. IA, GT and SA reduced to 0V, while Vcc
IO
stays on.
C10 C9 plus all VRs at PS4 or LPM. 24 MHz clock off
Table 4-3. Integrated Memory Controller (IMC) States
State Description
Power up CKE asserted. Active mode.
Pre-charge
Power down
CKE de-asserted (not self-refresh) with all banks closed.
Active Power
down
CKE de-asserted (not self-refresh) with minimum one bank active.
Self-Refresh CKE de-asserted using device self-refresh.
Table 4-4. PCI Express* Link States
State Description
L0 Full on – Active transfer state.
L1 Lowest Active Power Management – Longer exit latency
L3 Lowest power state (power-off) – Longest exit latency
Table 4-5. Direct Media Interface (DMI) States
State Description
L0 Full on – Active transfer state
L1 Lowest Active Power Management – Longer exit latency
L3 Lowest power state (power-off) – Longest exit latency