Data Sheet
Datasheet, Volume 1 of 2 7
2-35 Display Bit Per Pixel (BPP) Support .......................................................................... 51
2-36 Supported Resolutions for HBR (2.7 Gbps) by Link Width............................................ 51
2-37 Supported Resolutions for HBR2 (5.4 Gbps) by Link Width .......................................... 51
4-1 System States ....................................................................................................... 69
4-2 Processor IA Core / Package State Support ................................................................ 70
4-3 Integrated Memory Controller (IMC) States................................................................ 70
4-4 PCI Express* Link States......................................................................................... 70
4-5 Direct Media Interface (DMI) States.......................................................................... 70
4-6 G, S, and C Interface State Combinations .................................................................. 71
4-7 Deepest Package C-State Available ........................................................................... 78
4-8 Targeted Memory State Conditions ........................................................................... 81
4-9 Package C-States with PCIe* Link States Dependencies............................................... 82
5-1 Configurable TDP Modes.......................................................................................... 91
5-2 TDP Specifications (H/U-Processor Line) .................................................................... 99
5-3 Package Turbo Specifications (H/U-Processor Line) ..................................................... 99
5-4 Junction Temperature Specifications ....................................................................... 100
5-5 TDP Specifications (S-Processor Line) ..................................................................... 100
5-6 Low Power and TTV Specifications (S-Processor Line) ................................................ 101
5-7 Package Turbo Specifications (S-Processor Lines) ..................................................... 102
5-8 T
CONTROL
Offset Configuration (S-Processor Line - Client)........................................... 103
5-9 Thermal Margin Slope ........................................................................................... 104
6-1 Signal Tables Terminology ..................................................................................... 105
6-2 LPDDR3 Memory Interface..................................................................................... 105
6-3 DDR4 Memory Interface ........................................................................................ 106
6-4 System Memory Reference and Compensation Signals............................................... 108
6-5 PCI Express* Interface.......................................................................................... 108
6-6 DMI Interface Signals ........................................................................................... 108
6-7 Reset and Miscellaneous Signals............................................................................. 109
6-8 embedded DisplayPort* Signals.............................................................................. 110
6-9 Display Interface Signals ....................................................................................... 110
6-10 Processor Clocking Signals..................................................................................... 111
6-11 Testability Signals ................................................................................................ 111
6-12 Error and Thermal Protection Signals ...................................................................... 112
6-13 Power Sequencing Signals ..................................................................................... 112
6-14 Processor Power Rails Signals ................................................................................ 113
6-15 Processor Ground Rails Signals............................................................................... 114
6-16 GND, RSVD, and NCTF Signals ............................................................................... 115
6-17 Processor Internal Pull-Up / Pull-Down Terminations ................................................. 115
7-1 Processor Power Rails ........................................................................................... 116
7-2 Processor IA core (Vcc) Active and Idle Mode DC Voltage and Current Specifications ..... 117
7-3 Processor Graphics (Vcc
GT
) Supply DC Voltage and Current Specifications.................... 119
7-4 Memory Controller (VDDQ) Supply DC Voltage and Current Specifications .................... 121
7-5 System Agent (VccSA) Supply DC Voltage and Current Specifications .......................... 122
7-6 Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications............................ 123
7-7 VCC
OPC
,VCC
EOPIO
Voltage Levels ............................................................................ 124
7-8 Processor OPC (Vcc
OPC
), Processor EOPIO (Vcc
EOPIO
) Supply DC Voltage and Current
Specifications ...................................................................................................... 124
7-9 Processor OPC (Vcc
OPC_1p8
) Supply DC Voltage and Current Specifications ................... 124
7-10 Vcc Sustain (VccST) Supply DC Voltage and Current Specifications ............................. 125
7-11 Vcc Sustain Gated (VccSTG) Supply DC Voltage and Current Specifications .................. 125
7-12 Processor PLL (VccPLL) Supply DC Voltage and Current Specifications ......................... 126
7-13 Processor PLL_OC (VccPLL_OC) Supply DC Voltage and Current Specifications.............. 126
7-14 LPDDR3 Signal Group DC Specifications................................................................... 127
7-15 DDR4 Signal Group DC Specifications...................................................................... 128
7-16 PCI Express* Graphics (PEG) Group DC Specifications ............................................... 129