Data Sheet

Datasheet, Volume 1 of 2 51
Interfaces
2.5.13 Display Bit Per Pixel (BPP) Support
2.5.14 Display Resolution per Link Width
2.6 Platform Environmental Control Interface (PECI)
PECI is an Intel proprietary interface that provides a communication channel between
Intel processors and external components like Super IO (SIO) and Embedded
Controllers (EC) to provide processor temperature, Turbo, Configurable TDP, and
memory throttling control mechanisms and many other services. PECI is used for
platform thermal management and real time control and configuration of processor
features and performance.
Note: PECI over eSPI is supported on 8th Gen Intel
®
Core™ Processor-U 4+3e Only.
2.6.1 PECI Bus Architecture
The PECI architecture is based on a wired OR bus that the clients (as processor PECI)
can pull up (with strong drive).
The idle state on the bus is near zero.
The following figures demonstrate PECI design and connectivity:
• PECI Host-Clients Connection: While the host/originator can be third party PECI
host and one of the PECI client is a processor PECI device.
Table 2-35. Display Bit Per Pixel (BPP) Support
Technology Bit Per Pixel (bpp)
eDP* 24,30,36
DisplayPort* 24,30,36
HDMI* 24,36
Table 2-36. Supported Resolutions for HBR (2.7 Gbps) by Link Width
Link Width
Max Link Bandwidth
[Gbps]
Max Pixel Clock
(theoretical) [MHz]
U/H/S-Processor Lines
4 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp
2 lanes 5.4 180 2048x1280 @ 60 Hz, 24bpp
1 lane 2.7 90 1280x960 @ 60 Hz, 24bpp
Note: The examples assumed 60 Hz refresh rate and 24 bpp.
Table 2-37. Supported Resolutions for HBR2 (5.4 Gbps) by Link Width
Link Width
Max Link Bandwidth
[Gbps]
Max Pixel Clock
(theoretical) [MHz]
U/H/S-Processor Lines
4 lanes 21.6 720
Refer “Maximum Display
Resolutions” table
2 lanes 10.8 360 2880x1800 @ 60 Hz, 24bpp
1 lane 5.4 180 2048x1280 @ 60 Hz, 24bpp
Note: The examples assumed 60 Hz refresh rate and 24 bpp.