Data Sheet

Interfaces
32 Datasheet, Volume 1 of 2
• Full RX Equalization and acquisition for: AGC (Adaptive Gain Control), CDR (Clock
and Data Recovery), adaptive DFE (decision feedback equalizer) and adaptive CTLE
peaking (continuous time linear equalizer).
• Full adaptive phase 3 EQ compliant with PCI Express* Gen 3 specification.
Refer the PCI Express* Base Specification 3.0 for details on PCI Express* equalization.
2.3 Direct Media Interface (DMI)
Note: The DMI interface is only present in 2-Chip platform processors.
Direct Media Interface (DMI) connects the processor and the PCH.
Main characteristics:
• 4 lanes Gen 3 DMI support
• 8 GT/s point-to-point DMI interface to PCH
• DC coupling - no capacitors between the processor and the PCH
• PCH end-to-end lane reversal across the link
• Half-Swing support (low-power/low-voltage)
• DMI Supports L0s and L1 Link states (depending on the PCH SKU and support)
Note: Only DMI x4 configuration is supported.
2.3.1 DMI Lane Reversal and Polarity Inversion
Lane Reversal is only supported in PCH DMI Link, PCH DMI Lane Reversal is enabled or
disabled through SoftStrap.
Note: Polarity Inversion and Lane Reversal on DMI Link are not allowed in S-Processor Line
paired with Intel
®
200 (including X299) and Intel
®
Z370 Series Chipset Families.
Note: Polarity Inversion is supported on all the Receiver Lanes. Processor DMI will
autonomously detects the polarity inversion (Rx+ and Rx- is connected reversed)
based on the Training Sequence received and enabled it during Link Training.
Note: Processor DMI Lane Reversal is not supported, However PCH DMI Lane reversal is
supported refer
Figure 2-4, “Example for DMI Lane Reversal Connection” for more
information.