Data Sheet
Interfaces
30 Datasheet, Volume 1 of 2
• Power Management Event (PME) functions.
• Dynamic width capability.
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Lane reversal
• Full Advance Error Reporting (AER) and control capabilities are supported only on
Server SKUs.
The following table summarizes the transfer rates and theoretical bandwidth of PCI
Express* link.
Note: The processor has limited support for Hot-Plug. For details, refer to Section 4.4.
2.2.2 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug
and-Play specification. The processor PCI Express* ports support Gen 3.
At 8 GT/s, Gen3 operation results in twice as much bandwidth per lane as compared to
Gen 2 operation. The 16 lanes port can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.
Gen 3 PCI Express* uses a 128b/130b encoding which is about 23% more efficient
than the 8b/10b encoding used in Gen 1 and Gen 2.
The PCI Express* architecture is specified in three layers – Transaction Layer, Data Link
Layer, and Physical Layer. Refer the PCI Express Base Specification 3.0 for details of PCI
Express* architecture.
Table 2-13. PCI Express* Maximum Transfer Rates and Theoretical Bandwidth
PCI
Express*
Generation
Encoding
Maximum
Transfer Rate
[GT/s]
Theoretical Bandwidth [GB/s]
x1 x2 x4 x8 x16
Gen 1 8b/10b 2.5 0.25 0.5 1.0 2.0 4.0
Gen 2 8b/10b 5 0.5 1.0 2.0 4.0 8.0
Gen 3 128b/130b 8 1.0 2.0 3.9 7.9 15.8