Data Sheet

Datasheet, Volume 1 of 2 29
Interfaces
The processor supports the following:
Hierarchical PCI-compliant configuration mechanism for downstream devices.
Traditional PCI style traffic (asynchronous snooped, PCI ordering).
PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
Automatic discovery, negotiation, and training of link out of reset.
Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0: DMI -> PCI Express* Port 0.
64-bit downstream address format, but the processor never generates an address
above 512 GB (Bits 63:39 will always be zeros).
64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 512 GB (addresses where any of Bits 63:39 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 512 GB will be dropped.
Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status.
PCI Express* reference clock is 100-MHz differential clock.
Table 2-12. PCI Express* Bifurcation and Lane Reversal Mapping
Bifurcation
Link Width CFG Signals Lanes
0:1:0 0:1:1 0:1:2 CFG
[6]
CFG
[5]
CFG
[2]
0123456789101112131415
1x16 x16 N/A N/A
111
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1x16
Reversed
x16 N/A N/A
110
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2x8 x8 x8 N/A
101
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
2x8
Reversed
x8 x8 N/A
100
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
1x8+2x4 x8 x4 x4
001
0 1 2 3 4 5 6 7 0 1 2 3 0 1 2 3
1x8+2x4
Reversed
x8 x4 x4
000
3 2 1 0 3 2 1 0 7 6 5 4 3 2 1 0
Notes:
1. For CFG bus details, refer to Section 6.4.
2. Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration),
however further bifurcation is not supported.
3. In case that more than one device is connected, the device with the highest lane count, should always be connected to the
lower lanes, as follows:
Connect lane 0 of 1
st
device to lane 0.
Connect lane 0 of 2
nd
device to lane 8.
Connect lane 0 of 3
rd
device to lane 12.
For example:
a. When using 1x8 + 2x4, the 8 lane device should use lanes 0:7.
b. When using 1x4 + 1x2, the 4 lane device should use lanes 0:3, and other 2 lanes device should use lanes 8:9.
c. When using 1x4 + 1x2 + 1x1, 4 lane device should use lanes 0:3, two lane device should use lanes 8:9, one lane
device should use lane 12.
4. for reversal lanes, for example:
When using 1x8, the 8 lane device should use lanes 8:15, so lane 15 will be connected to lane 0 of the Device.