Data Sheet

Interfaces
28 Datasheet, Volume 1 of 2
2.1.11 DRAM Reference Voltage Generation
The memory controller has the capability of generating the LPDDR3 and DDR4
Reference Voltage (VREF) internally for both read and write operations. The generated
VREF can be changed in small steps, and an optimum VREF value is determined for
both during a cold boot through advanced training procedures in order to provide the
best voltage to achieve the best signal margins.
2.1.12 Data Swizzling
All Processor Lines does not have die-to-package DDR swizzling.
2.2 PCI Express* Graphics Interface (PEG)
Note: The processor’s PCI Express* interface is present only in 2-Chip platform processors.
This section describes the PCI Express* interface capabilities of the processor. Refer the
PCI Express Base* Specification 3.0 for details on PCI Express*.
2.2.1 PCI Express* Support
The processor’s PCI Express* interface is a 16-lane (x16) port that can also be
configured as multiple ports at narrower widths (Refer Table 2-12, Table 2-13).
The processor supports the configurations shown in the following table.