Data Sheet

Datasheet, Volume 1 of 2 27
Interfaces
2.1.9 Data Swapping
By default, the processor supports on-board data swapping in two manners (for all
segments and DRAM technologies):
byte (DQ+DQS) swapping between bytes in the same channel.
bit swapping within specific byte. ECC Byte swapping (with other Bytes) is not
allowed, ECC bits swap is allowed.
2.1.10 DRAM Clock Generation
Every supported rank has a differential clock pair. There are a total of four clock pairs
driven directly by the processor to DRAM.
DDR1 Byte0 DDR0 Byte2
DDR1 Byte1 DDR0 Byte3
DDR1 Byte2 DDR0 Byte6
DDR1 Byte3 DDR0 Byte7
DDR1 Byte4 DDR1 Byte2
DDR1 Byte5 DDR1 Byte3
DDR1 Byte6 DDR1 Byte6
DDR1 Byte7 DDR1 Byte7
Figure 2-2. Interleave (IL) and Non-Interleave (NIL) Modes Mapping
Table 2-11. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping (Sheet 2 of 2)
IL
(DDR4)
NIL
(DDR4, LPDDR3)
Channel Byte Channel Byte