Data Sheet

Interfaces
26 Datasheet, Volume 1 of 2
2.1.8 DDR I/O Interleaving
The processor supports I/O interleaving, which has the ability to swap DDR bytes for
routing considerations. BIOS configures the I/O interleaving mode before DDR training.
There are 2 supported modes:
• Interleave (IL)
• Non-Interleave (NIL)
The following table and figure describe the pin mapping between the IL and NIL modes.
4 66 41 61 84 34 152 20
7 60 42 9 88 50 161 49
8 67441697211621
11 36 47 23 98 38 164 17
13 27 49 63 100 54 168 33
14 3 50 47 104 5 176 44
16 68 52 14 112 52 193 8
19 55 56 30 128 71 194 24
21 10 64 70 131 22 196 40
22 29 67 6 133 58 200 56
25 45 69 42 134 13 208 19
26 57 70 62 137 28 224 11
28 0 73 12 138 41 241 7
31 15 74 25 140 48 242 31
32 69 76 32 143 43 244 59
35 39 79 51 145 37 248 35
Notes:
1. All other syndrome values indicate unrecoverable error (more than one error).
2. This table is relevant only for H-Processor ECC supported SKUs.
Table 2-10. ECC H-Matrix Syndrome Codes (Sheet 2 of 2)
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
Syndrome
Value
Flipped
Bit
Table 2-11. Interleave (IL) and Non-Interleave (NIL) Modes Pin Mapping (Sheet 1 of 2)
IL
(DDR4)
NIL
(DDR4, LPDDR3)
Channel Byte Channel Byte
DDR0 Byte0 DDR0 Byte0
DDR0 Byte1 DDR0 Byte1
DDR0 Byte2 DDR0 Byte4
DDR0 Byte3 DDR0 Byte5
DDR0 Byte4 DDR1 Byte0
DDR0 Byte5 DDR1 Byte1
DDR0 Byte6 DDR1 Byte4
DDR0 Byte7 DDR1 Byte5