Data Sheet

Interfaces
22 Datasheet, Volume 1 of 2
2.1.2 System Memory Timing Support
The IMC supports the following DDR Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
tCL = CAS Latency
tRCD = Activate Command to READ or WRITE Command delay
tRP = PRECHARGE Command Period
CWL = CAS Write Latency
Command Signal modes:
1N indicates a new DDR4 command may be issued every clock
2N indicates a new DDR4 command may be issued every 2 clocks
Table 2-6. Supported LPDDR3 x32 DRAMs Configurations(U/H-Processor Line)
Max
System
Capacity
PKG Type
(Dies bits
x PKG
Bits)
DRAM
Organization
/ PKG Type
Die
Density
PKG
Density
Dies Per
Channel
PKGs Per
Channel
Physical
Device
Rank
Banks
Inside
DRAM
Page
Size
2 GB SDP 32x32 128Mx32 4 Gb 4 Gb 2 2 1 8 8K
4 GB DDP 32x32 256Mx32 4 Gb 8 Gb 4 2 2 8 8K
8 GB QDP 16x32 512Mx32 4 Gb 16 Gb 8 2 2 8 8K
4 GB SDP 32x32 256Mx32 8 Gb 8 Gb 2 2 1 8 8K
8 GB DDP 32x32 512Mx32 8 Gb 16 Gb 4 2 2 8 8K
16 GB QDP 16x32 1024Mx32 8 Gb 32 Gb 8 2 2 8 8K
Notes:
1. x32 devices are 178 balls.
2. SDP = Single Die Package, DDP = Dual Die Package, QDP = Quad Die Package.
Table 2-7. Supported LPDDR3 x64 DRAMs Configurations(U-Processor Line)
Max
System
Capacity
PKG Type
(Dies bits
x PKG
Bits)
DRAM
Organization
/ PKG Type
Die
Density
PKG
Density
Dies Per
Channel
PKGs Per
Channel
Physical
Device
Rank
Banks
Inside
DRAM
Page
Size
2 GB DDP 32x64 128Mx64 4 Gb 8 Gb 2 1 1 8 8K
4 GB QDP 32x64 256Mx64 4 Gb 16 Gb 4 1 2 8 8K
4 GB DDP 32x64 256Mx64 8 Gb 16 Gb 2 1 1 8 8K
8 GB QDP 32x64 512Mx64 8 Gb 32 Gb 4 1 2 8 8K
Notes:
1. x64 devices are 253 balls.
2. SDP = Single Die Package, DDP = Dual Die Package, QDP = Quad Die Package.
Table 2-8. DRAM System Memory Timing Support (Sheet 1 of 2)
DRAM
Device
Transfer
Rate (MT/s)
tCL (tCK)
tRCD
(tCK)
tRP (tCK) CWL (tCK)
DPC
(SODIMM
Only)
CMD
Mode
DDR4 2133 15/16 14/15/16 15/16 11/14/14 1 or 2 1N/2N
DDR4 2400 17 17 17 12/16/16 1 or 2 2N