Data Sheet
Datasheet, Volume 1 of 2 129
Electrical Specifications
7.2.2.3 PCI Express* Graphics (PEG) DC Specifications
7.2.2.4 Digital Display Interface (DDI) DC Specifications
DDR_RCOMP[0] ODT resistance compensation
RCOMP values are memory topology
dependent.
6
DDR_RCOMP[1] Data resistance compensation 6
DDR_RCOMP[2] Command resistance compensation 6
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
IL
may experience excursions above V
DDQ
. However, input signal drivers should comply with the signal quality
specifications.
5. This is the pull up/down driver resistance after compensation. Note that BIOS power training may change these values
significantly based on margin/power trade-off. Refer processor I/O Buffer Models for I/V characteristics.
6. DDR_RCOMP resistance should be provided on the system board with ±1% resistors. DDR_RCOMP resistors are to V
SS
.
DDR_RCOMP resistors are installed on the package.
7. DDR_VREF is defined as V
DDQ
/2 for DDR4
8. R
ON
tolerance is preliminary and might be subject to change.
9. The value will be set during the MRC boot training within the specified range.
10. Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
11. Final value determined by BIOS power training, values might vary between bytes and/or units.
12. VREF values determined by BIOS training, values might vary between units.
13. VREF(INT) is a trainable parameter whose value is determined by BIOS for margin optimization.
14. DDR1_Vref_DQ connected to Channel 1 VREF_CA.
15. DDR_Vref_CA connected to Channel 0 VREF_CA.
Table 7-16. PCI Express* Graphics (PEG) Group DC Specifications
Symbol Parameter Min Typ Max Units Notes
1
Z
TX-DIFF-DC
DC Differential Tx Impedance 80 100 120 1, 5
Z
RX-DC
DC Common Mode Rx Impedance 40 50 60 1, 4
Z
RX-DIFF-DC
DC Differential Rx Impedance 80 — 120 1
PEG_RCOMP resistance compensation 24.75 25 25.25 2, 3
Notes:
1. Refer to the PCI Express Base Specification for more details.
2. Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
3. PEG_RCOMP resistance should be provided on the system board with 1% resistors. COMP resistors are to V
CCIO
.
PEG_RCOMP - Intel allows using 24.9 1% resistors.
4. DC impedance limits are needed to ensure Receiver detect.
5. The Rx DC Common Mode Impedance should be present when the Receiver terminations are first enabled to ensure that
the Receiver Detect occurs properly.Compensation of this impedance can start immediately and the 15 Rx Common Mode
Impedance (constrained by RLRX-CM to 50 ±20%) should be within the specified range by the time Detect is entered.
Table 7-17. Digital Display Interface Group DC Specifications (DP/HDMI*) (Sheet 1 of 2)
Symbol Parameter Min Typ Max Units Notes
1
V
OL
DDIB_TXC[3:0] Output Low Voltage
DDIC_TXC[3:0] Output Low Voltage
DDID_TXC[3:0] Output Low Voltage
— — 0.25*V
CCIO
V 1,2
V
OH
DDIB_TXC[3:0] Output High Voltage
DDIC_TXC[3:0] Output High Voltage
DDID_TXC[3:0] Output High Voltage
0.75*V
CCIO
— — V 1,2
Table 7-15. DDR4 Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter
USH-Processor Line
Units Notes
1
Min Typ Max