Data Sheet

Electrical Specifications
128 Datasheet, Volume 1 of 2
7.2.2.2 DDR4 DC Specifications
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. V
IH
and V
IL
may experience excursions above V
DDQ
. However, input signal drivers should comply with the signal quality
specifications.
5. This is the pull up/down driver resistance after compensation. Note that BIOS power training may change these values
significantly based on margin/power trade-off.
6. DDR_RCOMP resistance should be provided on the system board with ±1% resistors. DDR_RCOMP resistors are to V
SS
.
7. DDR_VREF is defined as V
DDQ
/2 for LPDDR3
8. R
ON
tolerance is preliminary and might be subject to change.
9. The value will be set during the MRC boot training within the specified range.
10. Processor may be damaged if V
IH
exceeds the maximum voltage for extended periods.
11. Final value determined by BIOS power training, values might vary between bytes and/or units.
12. VREF values determined by BIOS training, values might vary between units.
13. DDR0_VREF_DQ[1:0] / DDR0_VREF_DQ connected to Channel 0 VREF_DQ.
14. DDR0_VREF_DQ[1:0] is available in U processor line, DDR0_VREF_DQ is available in H/S processor line.
15. DDR1_VREF_DQ connected to Channel 1 VREF_DQ.
16. DDR_VREF_CA connected to both Channel 0 and 1 VREF_CA.
Table 7-15. DDR4 Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter
USH-Processor Line
Units Notes
1
Min Typ Max
V
IL
Input Low Voltage
— —
VREF(INT) -
0.07*VDDQ
V
2, 4, 8,
9, 13
V
IH
Input High Voltage VREF(INT)
+
0.07*VDDQ
— — V
3, 4, 8,
9, 13
R
ON_UP/DN(DQ)
DDR4 Data Buffer pull-up/ down Resistance Trainable  11
R
ODT(DQ)
DDR4 On-die termination equivalent
resistance for data signals
Trainable  11
V
ODT(DC)
DDR4 On-die termination DC working point
(driver set to receive mode)
0.45*V
DDQ
0.5*V
DDQ
0.55*V
DDQ
V 9
R
ON_UP/DN(CK)
DDR4 Clock Buffer pull-up/ down Resistance 0.8*Typ 26 1.2*Typ  5, 11
R
ON_UP/DN(CMD)
DDR4 Command Buffer pull-up/ down
Resistance
0.8*Typ 20 1.2*Typ  11
R
ON_UP/DN(CTL)
DDR4 Control Buffer pull-up/ down
Resistance
0.8*Typ 20 1.2*Typ  5, 11
R
ON_UP/DN
(DDR_VTT_CNTL)
System Memory Power Gate Control Buffer
Pull-Up/ down Resistance
40 — 140  -
I
LI
Input Leakage Current (DQ, CK)
0 V
0.2*V
DDQ
0.8*V
DDQ
— — 1 mA -
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VREF_CA
VREF output voltage
V
DDQ
/2-
0.06
V
DDQ
/2
V
DDQ
/
2+0.06
V
12,14,
15
Table 7-14. LPDDR3 Signal Group DC Specifications (Sheet 2 of 2)
Symbol Parameter
H and U -Processor Line
Unit Note
Min Typ Max