Data Sheet
Datasheet, Volume 1 of 2 127
Electrical Specifications
7.2.2 Processor Interfaces DC Specifications
7.2.2.1 LPDDR3 DC Specifications
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured on package pins as near as possible to the processor with an
oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum
length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
4. For Voltage less than 1V, TOB will be 50 mV.
Table 7-14. LPDDR3 Signal Group DC Specifications (Sheet 1 of 2)
Symbol Parameter
H and U -Processor Line
Unit Note
Min Typ Max
V
IL
Input Low Voltage — — 0.43*V
DDQ
V 2, 4, 8, 9
V
IH
Input High Voltage 0.57*V
DDQ
— — V 3, 4, 8, 9
R
ON_UP/DN(DQ)
LPDDR3 Data Buffer pull-up/ down
Resistance
Trainable 11
R
ODT(DQ)
LPDDR3 On-die termination equivalent
resistance for data signals
Trainable 11
V
ODT(DC)
LPDDR3 On-die termination DC working
point (driver set to receive mode)
0.45*V
DDQ
0.5*V
DDQ
0.55*V
DDQ
V 9
R
ON_UP/DN(CK)
LPDDR3 Clock Buffer pull-up/ down
Resistance
0.8*Typ 40 1.2*Typ 5, 11
R
ON_UP/DN(CMD)
LPDDR3 Command Buffer pull-up/ down
Resistance
0.8*Typ 40 1.2*Typ 11
R
ON_UP/DN(CTL)
LPDDR3 Control Buffer pull-up/ down
Resistance
0.8*Typ 23 1.2*typ 5, 11
R
ON_UP/DN
(DDR_VTT_CNTL)
System Memory Power Gate Control Buffer
Pull-Up Resistance
40 — 140 -
I
LI
Input Leakage Current (DQ, CK)
0V
0.2* V
DDQ
0.8*V
DDQ
— — 0.75 mA -
I
LI
Input Leakage Current (CMD,CTL)
0V
0.2*V
DDQ
0.8*V
DDQ
— — 0.9 mA -
DDR0_VREF_DQ[1:0]
DDR0_VREF_DQ
DDR1_VREF_DQ
DDR_VREF_CA
VREF output voltage Trainable V
DDQ
/2 Trainable V
12,13,14
,15,16
DDR_RCOMP[0] ODT resistance compensation
RCOMP values are memory topology
dependent.
6
DDR_RCOMP[1] Data resistance compensation 6
DDR_RCOMP[2] Command resistance compensation 6
Table 7-13. Processor PLL_OC (Vcc
PLL_OC
) Supply DC Voltage and Current Specifications
(Sheet 2 of 2)
Symbol Parameter Segment Min Typ Max
Un
it
Notes
1,2