Data Sheet
Datasheet, Volume 1 of 2 123
Electrical Specifications
7.2.1.5 Vcc
IO
DC Specifications
7.2.1.6 Vcc
OPC,
Vcc
EOPIO
DC Specifications
OPC VR output voltage is fixed to 1V, the processor can drive VR to LPM (Low Power
Mode) which sets VR output to 0V using ZVM# signal as shown in the following table.
Vcc
EOPIO
may be connected to OPC VR. The processor can drive VR to LPM (Low Power
Mode) which sets VR output to 0V using ZVM# signal (as shown in Table 7-8,
“Processor OPC (Vcc
OPC
), Processor EOPIO (Vcc
EOPIO
) Supply DC Voltage and Current
Specifications”).
Note: VccOPC, VccEOPIO and VccOPC_1P8 are unconnected for Processors without OPC
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured across Vcc
SA
_
SENSE
and Vss
SA
_
SENSE
as near as possible to the
processor with an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. PSx refers to the voltage regulator power state as set by the SVID protocol.
5. Vcc
SA
voltage during boot (Vboot)1.05V for a duration of 2 seconds.
6. LL measured at sense points.
7. LL specification values should not be exceeded. If exceeded, power, performance and reliability penalty are expected.
8. Load Line (AC/DC) should be measured by the VRTT tool and programmed accordingly via the BIOS Load Line override
setup options. AC/DC Load Line BIOS programming directly affects operating voltages (AC) and power measurements
(DC). A superior board design with a shallower AC Load Line can improve on power, performance, and thermals compared
to boards designed for POR impedance.
9. For Voltage less than 1V, TOB will be 50 mV.
Table 7-6. Processor I/O (Vcc
IO
) Supply DC Voltage and Current Specifications
Symbol Parameter Segment Min Typ Max Unit
Note
1,2
Vcc
IO
Voltage for the memory controller
and shared cache
UHS
—
0.95
—V 3
TOB
VCCIO
Vcc
IO
Tolerance
All +/-5 (AC + DC + Ripple)
Up to 1 MHz
%
3,5
Icc
MAX_VCCIO
Max Current for V
CCIO
Rail
U
H
S
—
—
—
—
—
—
3.6
6.4
6.4
A-
T_OVS_MAX Max Overshoot time All — — 150 S4
V_OVS_MAX Max Overshoot at TDP All — — 30 mV 4
Notes:
1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These
specifications will be updated with characterized data from silicon measurements at a later date.
2. Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
3. The voltage specification requirements are measured across Vcc
IO
_
SENSE
and Vss
IO
_
SENSE
as near as possible to the
processor with an oscilloscope set to 100-MHz bandwidth, 1.5 pF maximum probe capacitance, and 1 M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the
system is not coupled into the oscilloscope probe.
4. OS occurs during power on only, not during normal operation
5. For Voltage less than 1v, TOB will be +/-50mV (AC + DC + Ripple) up to 1 MHz.
Table 7-5. System Agent (Vcc
SA
) Supply DC Voltage and Current Specifications (Sheet 2
of 2)
Symbol Parameter Segment Min Typ Max Unit
Note
1,
2