Data Sheet

Datasheet, Volume 1 of 2 113
Signal Description
6.11 Processor Power Rails
PROC_DETECT#
/SKTOCC#
Processor Detect / Socket Occupied: Pulled
down directly (0 Ohms) on the processor
package to the ground. There is no connection
to the processor silicon for this signal. System
board designers may use this signal to
determine if the processor is present.
N/A N/A SE All Processor Lines
VIDSOUT
VIDSCK
VIDALERT#
VIDSOUT, VIDSCK, VIDALERT#: These
signals comprise a three-signal serial
synchronous interface used to transfer power
management information between the
processor and the voltage regulator controllers.
I/O
O
I
I:GTL/O:OD
OD
CMOS
SE All Processor Lines
PM_SYNC
Power Management Sync: A sideband signal
to communicate power management status
from the PCH to the processor. PCH report
EXTTS#/EVENT# status to the processor.
I CMOS SE
H and S-Processor
Line
PM_DOWN
Power Management Down: Sideband to
PCH. Indicates processor wake up event
EXTTS# on PCH. The processor combines the
pin status into the OLTM/CLTM.
O CMOS SE
H and S-Processor
Line
MSM#
Minimum Speed Mode: Control signal to
VccEOPIO VR (connected only in 2 VR solution
for OPC).
O CMOS SE
Processors w/ On-
Package Cache
ZVM#
Zero Voltage Mode: Control Signal to OPC VR,
when low OPC VR output is 0V.
O CMOS SE
Processors w/ On-
Package Cache
Table 6-14. Processor Power Rails Signals (Sheet 1 of 2)
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
Vcc Processor IA cores power rail I Power — All Processor Lines
Vcc
GT
Processor Graphics power rail I Power — All Processor Lines
V
DDQ
System Memory power rail I Power — All Processor Lines
Vcc
SA
Processor System Agent power rail I Power — All Processor Lines
Vcc
IO
Processor I/O power rail. Consists of V
CCIO
and
Vcc
IO_DDR
. V
CCIO
and V
CCIO_DDR
should be isolated
from each other.
I Power — All Processor Lines
Vcc
ST
Sustain voltage for processor standby modes I Power — All Processor Lines
Vcc
STG
Gated sustain voltage for processor standby modes I Power — U/H-Processor Lines
Vcc
PLL
Processor PLLs power rails
I Power — All Processor Lines
Vcc
PLL_OC
I Power — All Processor Lines
Vcc
OPC
Processor OPC power rails
Note: Unconnected for Processors without OPC.
I Power -
Processors w/ On-
Package Cache
Vcc
OPC_1p8
I Power -
Processors w/ On-
Package Cache
Vcc
EOPIO
I Power -
Processors w/ On-
Package Cache
Table 6-13. Power Sequencing Signals (Sheet 2 of 2)
Signal Name Description Dir. Buffer Type
Link
Type
Availability