Data Sheet

Signal Description
112 Datasheet, Volume 1 of 2
6.9 Error and Thermal Protection Signals
6.10 Power Sequencing Signals
Table 6-12. Error and Thermal Protection Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
CATERR#
Catastrophic Error: This signal indicates that the
system has experienced a catastrophic error and
cannot continue to operate. The processor will set this
signal for non-recoverable machine check errors or
other unrecoverable internal errors. CATERR# is used
for signaling the following types of errors: Legacy
MCERRs, CATERR# is asserted for 16 BCLKs. Legacy
IERRs, CATERR# remains asserted until warm or cold
reset.
O OD SE All Processor Lines
PECI
Platform Environment Control Interface: A serial
sideband interface to the processor. It is used
primarily for thermal, power, and error management.
I/O
PECI,
Async
SE All Processor Lines
PROCHOT#
Processor Hot: PROCHOT# goes active when the
processor temperature monitoring sensor(s) detects
that the processor has reached its maximum safe
operating temperature. This indicates that the
processor Thermal Control Circuit (TCC) has been
activated, if enabled. This signal can also be driven to
the processor to activate the TCC.
I/O
GTL I
OD O
SE All Processor Lines
THERMTRIP#
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal thermal
sensor. This sensor is set well above the normal
operating temperature to ensure that there are no
false trips. The processor will stop all executions when
the junction temperature exceeds approximately
130 °C. This is signaled to the system by the
THERMTRIP# pin.
O OD SE All Processor Lines
Table 6-13. Power Sequencing Signals (Sheet 1 of 2)
Signal Name Description Dir. Buffer Type
Link
Type
Availability
PROCPWRGD
Processor Power Good: The processor
requires this input signal to be a clean
indication that the V
CC
and V
DDQ
power supplies
are stable and within specifications. This
requirement applies regardless of the S-state of
the processor. 'Clean' implies that the signal will
remain low (capable of sinking leakage
current), without glitches, from the time that
the power supplies are turned on until they
come within specification. The signal should
then transition monotonically to a high state.
I CMOS SE All Processor Lines
VCCST_PWRGD
VCCST Power Good: The processor requires
this input signal to be a clean indication that
the VCCST and VDDQ power supplies are stable
and within specifications. This signal should
have a valid level during both S0 and S3 power
states. 'Clean' implies that the signal will
remain low (capable of sinking leakage
current), without glitches, from the time that
the power supplies are turned on until they
come within specification. The signal should
then transition monotonically to a high state.
I CMOS SE All Processor Lines