Data Sheet

Datasheet, Volume 1 of 2 111
Signal Description
6.7 Processor Clocking Signals
6.8 Testability Signals
Table 6-10. Processor Clocking Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
BCLKP
BCLKN
100 MHz Differential bus clock input to the processor I Diff
H and S-Processor
Line
CLK24P
CLK24N
24 MHz Differential bus clock input to the processor I Diff
PCI_BCLKP
PCI_BCLKN
100 MHz Clock for PCI Express* logic I Diff
Table 6-11. Testability Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
BPM#[3:0]
Breakpoint and Performance Monitor Signals:
Outputs from the processor that indicate the status
of breakpoints and programmable counters used for
monitoring processor performance.
I/O GTL SE All Processor Lines
PROC_PRDY#
Probe Mode Ready: PROC_PRDY# is a processor
output used by debug tools to determine processor
debug readiness.
O OD SE All Processor Lines
PROC_PREQ#
Probe Mode Request: PROC_PREQ# is used by
debug tools to request debug operation of the
processor.
I GTL SE All Processor Lines
PROC_TCK
Test Clock: This signal provides the clock input for
the processor Test Bus (also known as the Test
Access Port). This signal should be driven low or
allowed to float during power on Reset.
I GTL SE All Processor Lines
PROC_TDI
Test Data In: This signal transfers serial test data
into the processor. This signal provides the serial
input needed for JTAG specification support.
I GTL SE All Processor Lines
PROC_TDO
Test Data Out: This signal transfers serial test data
out of the processor. This signal provides the serial
output needed for JTAG specification support.
O OD SE All Processor Lines
PROC_TMS
Test Mode Select: A JTAG specification support
signal used by debug tools.
I GTL SE All Processor Lines
PROC_TRST#
Test Reset: Resets the Test Access Port (TAP) logic.
This signal should be driven low during power on
Reset.
I GTL SE All Processor Lines