Data Sheet

Signal Description
110 Datasheet, Volume 1 of 2
6.5 embedded DisplayPort* (eDP*) Signals
6.6 Display Interface Signals
Table 6-8. embedded DisplayPort* Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
eDP_TXP[3:0]
eDP_TXN[3:0]
embedded DisplayPort* Transmit: differential
pair.
O eDP Diff All Processor Lines
eDP_AUXP
eDP_AUXN
embedded DisplayPort* Auxiliary: Half-duplex,
bidirectional channel consist of one differential pair.
O eDP Diff All Processor Lines
DISP_UTILS
embedded DisplayPort* Utility: Output control
signal used for brightness correction of embedded
LCD displays with backlight modulation.
This pin will co-exist with functionality similar to
existing BKLTCTL pin on PCH
O
Async
CMOS
SE All Processor Lines
DISP_RCOMP
DDI IO Compensation resistor, supporting
DP*, eDP* and HDMI* channels.
N/A A SE All Processor Lines
Note:
1. When using eDP bifurcation:
— x2 eDP lanes for eDP panel (eDP_TXP[0:1], eDP_TXN[0:1])
— x2 lanes for DP (eDP_TXP[2:3], eDP_TXN[2:3])
Table 6-9. Display Interface Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
(2)
DDI1_TXP[3:0]
DDI1_TXN[3:0]
DDI2_TXP[3:0]
DDI2_TXN[3:0]
DDI3_TXP[3:0]
DDI3_TXN[3:0]
Digital Display Interface Transmit:
Differential Pairs
O
DP/
HDMI*
Diff
All Processor Lines.
DDI3_TXP[3:0]
DDI3_TXN[3:0]
DDI3_AUXP
DDI3_AUXN
are present in H and
S-Processor Line.
DDI1_AUXP
DDI1_AUXN
DDI2_AUXP
DDI2_AUXN
DDI3_AUXP
DDI3_AUXN
Digital Display Interface Display Port
Auxiliary: Half-duplex, bidirectional
channel consist of one differential pair for
each channel.
O
DP/
HDMI*
Diff
Notes:
1. N/A
2. DDI3_AUXN and DDI3_AUXP are valid in U-Processor Line but should be considered as reserved pins.