Data Sheet

Datasheet, Volume 1 of 2 109
Signal Description
6.4 Reset and Miscellaneous Signals
Table 6-7. Reset and Miscellaneous Signals
Signal Name Description Dir.
Buffer
Type
Link
Type
Availability
CFG[19:0]
Configuration Signals: The CFG signals have a
default value of '1' if not terminated on the board.
Intel recommends placing test points on the board
for CFG pins.
CFG[0]: Stall reset sequence after PCU PLL
lock until de-asserted:
1 = (Default) Normal Operation; No
stall.
0 = Stall.
CFG[1]: Reserved configuration lane.
CFG[2]: PCI Express* Static x16 Lane
Numbering Reversal.Reserved
1 = Normal operation
0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
CFG[4]: eDP enable:
1 = Disabled.
0 = Enabled.
CFG[6:5]: PCI Express* BifurcationReserved
00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
CFG[7]: PEG Training:Reserved
1 = (default) PEG Train immediately
following RESET# de assertion.
0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration lanes.
I GTL SE
All Processor Lines.
CFG[2], CFG[6:5] and
CFG[7] are relevant
for H and S-Processor
Line only and test
point may be placed
on the board for them.
CFG_RCOMP Configuration Resistance Compensation N/A N/A SE All Processor Lines
PROC_POPIRCOMP POPIO Resistance Compensation N/A N/A SE U-Processor Line
RESET#
Platform Reset pin driven by the PCH.
I CMOS SE
H and S-Processor
Line
PROC_SELECT#
Processor Select: This pin is for compatibility
with future platforms. It should be unconnected
for this processor.
N/A
H and S-Processor
Line
PROC_TRIGIN
Debug pin
I CMOS SE
H and S-Processor
Line
PROC_TRIGOUT
Debug pin
O CMOS SE
H and S-Processor
Line
PROC_AUDIO_SDI
Processor Audio Serial Data Input: This signal
is an input to the processor from the PCH.
I AUD SE
H and S-Processor
Line PROC_AUDIO_SDO
Processor Audio Serial Data Output: This
signal is an output from the processor to the PCH.
O AUD SE
PROC_AUDIO_CLK Processor Audio Clock I AUD SE
IST_TRIG
Impedance Spectrum Tool Trigger: trigger
point to support debug of possible power issues.
O GTL SE
U and H-Processor
Line