User Manual

14 Specification Update
HSH16 System May Hang When Using the TPH Prefetch Hint
Problem: When all enabled cores on a socket are simultaneously in core C3, core C6, or package
C6 state and a PCIe* TPH (Transaction layer packet Processing Hint) with the prefetch
hint set is received, the system may hang.
Implication: Due to this erratum, the system may hang.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH17 TS1s Do Not Convey The Correct Transmitter Equalization Values
During Recovery.RcvrLock
Problem: The PCIe* 3.1 Base Specification requires that TS1s sent during Recovery.RcvrLock
following 8.0 GT/s EQ (adaptive equalization) contain the final transmitter preset
number and coefficient values that were requested by an endpoint during phase 2 of
EQ. Due to this erratum, TS1s with incorrect transmitter preset number values may be
sent during Recovery.RcvrLock following 8.0 GT/s adaptive equalization.
Implication: Endpoints that check these values may, when unexpected values are found, request
equalization restart in subsequent TSs it sends. If EQ requests from the endpoint are
supported in the BIOS or OS, EQ will be restarted and the link may continue this EQ
loop indefinitely.
Workaround: None identified.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH18 MSR_TEMPERATURE_TARGET MSR May Read as '0'
Problem: Due to this erratum, reading the MSR_TEMPERATURE_TARGET MSR (1A2H) may
incorrectly return '0'.
Implication: Software that depends on the contents of the MSR_TEMPERATURE_TARGET MSR may
not behave as expected.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the affected steppings, see the Summary Tables of Changes.
HSH19 PECI RdIAMSR() Command May Fail After Core C6 State is Entered
Problem: Reading core Machine Check Bank registers using the PECI (Platform Environment
Control Interface) RdIAMSR() command may fail after core C6 state has been entered.
Implication: Invalid data may be returned when using PECI to read core Machine Check Bank
registers.
Workaround: It is possible for the BIOS to contain a workaround for this erratum
Status: For the affected steppings, see the Summary Tables of Changes.
HSH20 CLTT May Cause BIOS To Hang On a Subsequent Warm Reset
Problem: If CLTT (Closed Loop Thermal Throttling) is enabled when a warm reset is requested,
due to this erratum, the processor will resume DIMM temperature polling before the
memory sub-system has been re-initialized.
Implication: This erratum may lead to a BIOS hang. The warm reset request will fail, along with
subsequence warm reset attempts. The failing condition is cleared by a cold reset.
Workaround: A BIOS workaround has been identified. Please refer to the latest version of the
Platform Reference Code (RC).
Status: For the affected steppings, see the Summary Tables of Changes.